Electrical & Computer Engineering

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    Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach
    (2011) Lauenstein, Jean-Marie; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR susceptibility is explored. SEGR evaluation of gamma-irradiated power MOSFETs suggests a non-significant SEGR susceptibility enhancement due to accumulated dose from gamma rays. During SEGR testing, an unexpected enhanced dose effect from heavy-ion irradiation was detected. We demonstrate that this effect could be due to direct ionization by two or more ions at the same channel location. The probability on-orbit for such an occurrence is near-zero given the low heavy-ion fluence over a typical mission lifetime, and did not affect SEGR susceptibility. The results of this work can be used to bound the risk of SEGR in power MOSFETs considered for insertion into spacecraft and instruments.
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    Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics
    (2010) Holloway, Michael Andrew; O'Shea, Patrick G; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity.
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    On The Pointing And Jitter Characterization Of MEMS Two-Axis (Tip-Tilt) Mirrors
    (2007-10-08) Edwards, Clinton Lee; Davis, Christoper C; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    This dissertation presents three first-principles analytic, closed-form models that describe the pointing characteristics of MEMS Two-Axis (Tip-Tilt) Mirrors: (1) a 2D Torque Model, (2) a Micro-mirror Pointing Model (MPM), and (3) a Micro-mirror Jitter Model (MJM). The 2D Torque Model accounts for all of the fundamental electrodynamics inherent in the operation of a MEMS Two-Axis (Tip-Tilt) Mirror. The 2D Torque Model is utilized in the MPM model and the MJM model and is a function of both axis angles. These three models provide explicit relationships between MEMS mirror physical, electrical, and environmental design parameters, and mirror performance. The MPM model, consisting of coupled damped harmonic oscillators with the 2D Torque Model as an input, is used to analyze the dynamics of the mirror. This formulation is imposed by Euler equations and the mirror's rigid structure. A generalized torque function, "G", is presented that utilizes symmetry in the torsional expressions to facilitate software implementation. A methodology is explained for determining the dynamic constants for the mirror as well as an "effective length" which accounts for electric field fringing. Since MEMS fabrication leads to variations in physical properties, the MPM model can be calibrated for a particular mirror to compensate for this variation. Experimental measurements and the MPM model results are in close agreement for steady-state and transient mirror dynamics. The MJM model was created using the MPM model to address the effects of mirror facet jitter. The MJM model provides an explicit relationship between noise sources and the resulting mirror jitter. It can be used to simulate the effects of mirror jitter as a function of the originating noise sources which are: (1) control voltage fluctuation, (2) platform vibration, (3) Brownian motion noise. A methodology is developed to validate the MJM model. Measurements from the resulting experimental apparatus support the model. Additionally, the experimental apparatus permitted pressure dependent measurements to be made. Mirror jitter was recorded and analyzed for varying pressure and tip-tilt angles. Damping constants (for both axes) were measured. Brownian motion generated jitter was isolated and its variance observed to be pressure invariant as the model predicted.
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    Thermal and performance modeling of nanoscale mosfets, carbon nanotube devices and integrated circuits
    (2006-05-31) Akturk, Akin; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    We offer new paradigms for electronic devices and digital integrated circuits (ICs) in an effort to overcome important performance threatening problems such as self heating. To investigate chip heating, we report novel methods for predicting the thermal profiles of complex ICs at the resolution of a single device. We resolve device and IC temperatures self-consistently, with individual device performances, while accounting for IC layout and software application details. At the device level, we calculate performance and generated heat details. We then extend these performance figures to the overall chip using a stochastic or Monte Carlo type methodology. Next, at the IC level, we solve for the device temperatures using the chip's layout and application software details. Here, we apply our mixed-mode algorithm to two-dimensional (planar) and three-dimensional ICs. To relieve thermal stresses and performance degradation in specific areas of extreme heating or hot spots, we offer design strategies using thermal contacts or different IC layouts. Moreover, we also show chips that we had designed and fabricated through IC fabrication clearing house MOSIS for experimental investigations. We also investigate carbon nanotubes (CNTs) and CNT embedded MOSFETs as new device paradigms for future electronic circuits. To examine the effects of CNTs on device performance, we develop a CNT Monte Carlo simulator, and determine scattering rates and CNT electron transport. Here, we report position-dependent velocity oscillations and length effects in semiconducting single-walled zig-zag carbon nanotubes. Our calculated results indicate velocity oscillations in the Terahertz range, which approaches phonon frequencies. This may facilitate new high frequency RF device and circuit designs, opening new paradigms in communication networks. Furthermore, to obtain device performance figures for MOSFETs that embed CNTs in their channels, our device solver determines interactions between the CNT and silicon (Si) by obtaining quantization and transport effects on the tube and the Si, and at the CNT-Si barrier. We predict that the CNT-MOSFET yields a better performance than the traditional MOSFET. Especially, CNT-MOSFETs employing lower diameter tubes exhibit improved performance capabilities. We also perform similar analyses for CNT embedded SOI-MOSFETs.
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    INTEGRATED INPUT MODELING AND MEMORY MANAGEMENT FOR IMAGE PROCESSING APPLICATIONS
    (2005-12-07) Haim, Fiorella; Bhattacharyya, Shuvra S; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Image processing applications often demand powerful calculations and real-time performance with low power and energy consumption. Programmable hardware provides inherent parallelism and flexibility making it a good implementation choice for this application domain. In this work we introduce a new modeling technique combining Cyclo-Static Dataflow (CSDF) base model semantics and Homogeneous Parameterized Dataflow (HPDF) meta-modeling framework, which exposes more levels of parallelism than previous models and can be used to reduce buffer sizes. We model two different applications and show how we can achieve efficient scheduling and memory organization, which is crucial for this application domain, since large amounts of data are processed, and storing intermediate results usually requires the use of off-chip resources, causing slower data access and higher power consumption. We also designed a reusable wishbone compliant memory controller module that can be used to access the Xilinx Multimedia Board's memory chips using single accesses or burst mode.