UMD Theses and Dissertations
Permanent URI for this collectionhttp://hdl.handle.net/1903/3
New submissions to the thesis/dissertation collections are added automatically as they are received from the Graduate School. Currently, the Graduate School deposits all theses and dissertations from a given semester after the official graduation date. This means that there may be up to a 4 month delay in the appearance of a given thesis/dissertation in DRUM.
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Item PERFORMANCE ENHANCEMENTS OF MICRO CORIOLIS VIBRATORY GYROSCOPES THROUGH LINEARIZED TRANSDUCTION AND TUNING MECHANISMS(2023) Knight, Ryan; DeVoe, Don L; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)A quadruple mass Microelectromechanical System (MEMS) Coriolis vibratory gyroscope has been re-engineered with the singular focus of minimizing nonlinear transduction mechanisms, thereby allowing for angle random walk (ARW) noise reduction when operating at amplitudes higher than 2 μm. The redesign involved six primary steps: (i) the creation of an aspect-ratio independent deep reactive ion etch with minimal notching on 100 μm thick silicon-on-insulator device layer, (ii) the creation of micro-torr vacuum packaging capability, enabling operation at the thermoelastic dissipation limit of silicon, (iii) the redesign of Coriolis mass folded flexures and shuttle springs, (iv) the linearization of the antiphase coupler spring rate while maintaining parasitic modal separation, (v) the substitution of parallel plate transducers with linear combs, and (vi) the implementation of dedicated force-balanced electrostatic frequency tuners. Cross-axis stiffness is also reduced through folded-flexure moment balancing to further reduce ARW. By balancing positive and negative Duffing frequency contributions, net fractional frequency nonlinearity was reduced to -20 ppm. The gyroscope presented in this research has achieved, a first reported of its kind, an ARW of 0.0005 °/√hr, with an uncompensated bias instability of 0.08 °/hr. These advancements hold promise for enhancing navigation and North-finding applications. In tandem with gyroscope performance enhancements, vacuum packaging of ceramic chip carrier physics packages has achieved pressure levels below 1 micro-torr, a first in the field and remains state-of-the-art. Besides high-performance MEMS inertial sensors, ultrahigh vacuum packaging proves beneficial for chip scale atomic clocks, which require micro-torr vacuum levels to maintain fractional frequencies less than 10^-12. Finally, an approach to tuning the quality factor mismatch between degenerate modes in as-fabricated gyroscopes has demonstrated a reduction in gyroscope bias instability. This tuning can be achieved by incorporating lead zirconate titanate into regions where the trade-off between mechanical Q, tuning Q, and bias instability reduction is balanced. Both modeling and empirical frequency data justify this approach, suggesting, for typical MEMS foundry Q mismatch of 7%, a 70× reduction in bias instability.Item A BARE-DIE SIC-BASED ELECTRO-THERMALLY CO-DESIGNED WIRE-BONDLESS HIGH-FREQUENCY DC-DC CONVERTER(2021) Park, Yongwan; Khaligh, Alireza; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)The current technological status of switch-mode power converters requires a paradigm shift to enable a substantial enhancement in power density. The emergence of wide-bandgap (WBG) devices such as Silicon Carbide (SiC) MOSFETs o↵ers the possibility to achieve high power-density by enabling higher switching frequency and higher temperature operation. This dissertation addresses the following shortcomings of conventional designs: 1) High values of commutation loop inductances and parasitic capacitances which prohibit fast, reliable and efficient switching performance, 2) inadequate thermal design capable of handling very high heat-fluxes (exceeding hundreds of W/cm2), which naturally stem from highly compact design and high allowable losses of the SiC devices, and 3) decoupled and sequential electrical and thermal designs, which leads to sub-optimal electro-thermal performance. As a solution to these challenges, this dissertation investigates two design strategies: 1) a novel switch module structure with low parasitics, and 2) a novel planar transformer structure with integrated leakage inductance and cooling system. Both approaches result in enhanced thermal performance, optimized through simultaneous electro-thermal co-design. A common key highlight of the proposed solutions is the high degree of integration realized by use of sub-components that integrate both electrical and thermal performance. This will save real estate by reducing component count and by lessening electrical and thermal burdens. In the first part of this dissertation, a detailed electrical characterization of a novel, wire-bondless, three-dimensional (3D), half-bridge switch module using bare-die SiC MOSFETs is presented. The switch assembly features the use of electro- thermally multi-functional components, simultaneously serving as bus-bars and heat sinks. A highly compact composition with embedded decoupling capacitors and gate driver components is realized with vertical loop structures for both power and gate drive circuits. Besides, the wire-bondless structure enables double-sided cooling, which significantly improves the thermal performance. 3D finite element analysis simulations and experiments demonstrate that the proposed switch module can achieve extremely low values of parasitic loop inductances (Lloop,power = 1.35 nH, Lloop,gate = 5.1 nH at a parasitic oscillation frequency of 100 MHz) as well as high thermal performance without entailing significant layout capacitances and resistances. The second part of this dissertation proposes an electro-thermal design optimization method of a high-frequency planar transformer with an integrated leakage inductance and thermal management system. Aiming at the use in a high-frequency (>500 kHz) dual-active-bridge (DAB) converter, an optimal leakage inductance selection process is explored based on highly accurate analyses of the DAB converter operation for maximizing the efficiency. Effect of design variables like the number of turns of the transformer and cooler height on the transformer’s electrical parameters such as leakage inductance, ac resistance and parasitic capacitance is further analyzed in detail. The dependence of converter efficiency on these parameters is estimated using realistic simulations and analyses, and potential trade-o↵s of the design are investigated. Thermal modeling is used to evaluate the thermal performance of different designs. Based on a combination of the analyses, optimal designs are identified, which simultaneously ensure good electrical and thermal performance. Finally, a compact DAB converter is designed based on the investigated components, operating at a switching frequency of 500 kHz. Robust gate-driver circuitry and auxiliary parts are also developed to tolerate such high switching frequency as well as high dv/dt. The optimal design processes, operation strategies and analytical models are validated through diverse experiments on 3.3 kW dc-dc converter operation. As a result of the investigations, the converter achieves zero-voltage-switching over various load conditions with satisfactory high-frequency waveforms and a peak efficiency of 98%. The converter’s operation at high power is validated through a designed loss-emulation test corresponding to 8.4 kW operation.Item A THERMOMECHANICAL FATIGUE LIFE PREDICTION METHODOLOGY FOR BALL GRID ARRAY COMPONENTS WITH REWORKABLE UNDERFILL(2019) Serebreni, Maxim; McCluskey, Patrick; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Underfill materials were originally developed to improve the thermo-mechanical reliability of flip-chip devices due to the large coefficient of thermal expansion (CTE) mismatch between the silicon die and substrate. More recently, underfill materials, specifically reworkable underfills, have been used to improve reliability of second level interconnects in ball grid array (BGA) packages in harsh end-use environments such as automotive, military and aerospace. In these environments, electronic components are exposed to mechanical shock, vibration, and large fluctuations in temperatures. Although reworkable underfills improve the reliability of BGA components under mechanical shock and vibration, some reworkable underfills have been shown to reduce reliability during thermal cycling environments. Consequently, this research employs experimental and numerical approaches to investigate the impact of reworkable underfill materials on thermomechanical fatigue life of solder joints in BGA packages. In the first section of the analysis, material characterization of a reworkable underfill is performed to determine appropriate material models for reworkable underfills. In the second analysis section, a variety of underfill materials with different properties are exposed to harsh and benign thermal cycles to determine the stress state responsible for reducing fatigue life of solder joints in BGA packages. In the final analysis section, simulations are performed on the BGAs with reworkable underfill to develop a fatigue life predication methodology that implements a modified mode separation scheme. The model developed in this work provides a working fatigue life approach for BGA packages with reworkable underfills exposed to thermal loading. The results of this study can be utilized by the automotive, military, and aerospace industries to optimize underfill material selection process and provide reliability assessment of BGA components in real world environments.Item EFFECTS OF GLASS/EPOXY INTERPHASES ON ELECTRO-CHEMICAL FAILURES IN PRINTED CIRCUIT BOARDS(2018) Sood, Bhanu Pratap; Pecht, Michael G; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Reduction in printed circuit board line spacing and via diameters and the increased density of vias with higher aspect ratios (ratio between the thickness of the board and the size of the drilled hole before plating) are making electronic products increasingly more susceptible to material and manufacturing defects. One failure mechanism of particular concern is conductive anodic filament formation, which typically occurs in two steps: degradation of the resin/glass fiber bond followed by an electrochemical reaction. The glass-resin bond degradation provides a path along which electrodeposition occurs due to electrochemical reactions. Once a path is formed, an aqueous layer, which enables the electrochemical reactions to take place, can develop through the adsorption, absorption, and capillary action of moisture at the resin/fiber interphase. This study describes the experimental and analytical work undertaken to understand the glass-resin delamination and the methods used for analyzing this critical interphase. This study shows that a smaller conductor spacing in reduces the time to failure due to conductive anodic filament formation and that the plated-through-hole to plated-through-hole conductor geometry is more susceptible to conductive anodic filament-induced failures than plated through hole to plane geometries. The results also show that laminates with similar materials and geometries with a 45-degree angle of weave demonstrate a higher resistance to conductive anodic filament formation compared with a 90-degree angle of weave. The study is the first of its kind conducted on FR-4 printed circuit board materials where the pathway formation due to breakage of the organosilane bonds at the glass/resin interphase was evaluated. Using techniques such as force spectroscopy, micro-Fourier transform infrared spectroscopy, scanning quantum interface device microscopy and focused ion beam, evidence of bond breakage and a pathway formation was revealed, poor glass treatment, hydrolysis of the silane glass finish (adsorption of water at the glass fiber/epoxy resin interphase) or repeated thermal cycling contribute to the bond breakage. The technique of applying in-situ resistance measurements during cross-sectioning analysis of printed circuit boards suspected of conductive anodic filament is the first time this method is described in the open literature. This solution addresses the potential problem in destructive physical analysis of grinding away the evidence of the CAF filament and ultimately loosing evidence at the failure site. By applying a subset of the evaluation criteria described in this research, an upfront evaluation of printed circuit board materials can be performed for susceptibility to electro-chemical migration and other failure causes in PCBs that are attributable to the glass/resin interfacial adhesion. Manufacturers can identify board suppliers based on answers to and validation of a series of questions. These questions focus on the necessary requirements of reliable board material manufacturing and are independent of the specifications of the product.Item Detection of Interconnect Failure Precursors using RF Impedance Analysis(2010) Kwon, Daeil; Pecht, Michael G; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Many failures in electronics result from the loss of electrical continuity of common board-level interconnects such as solder joints. Measurement methods based on DC resistance such as event detectors and data-loggers have long been used by the electronics industry to monitor the reliability of interconnects during reliability testing. DC resistance is well-suited for characterizing electrical continuity, such as identifying an open circuit, but it is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates towards the interior. A partially degraded interconnect can cause the RF impedance to increase due to the skin effect, a phenomenon wherein signal propagation at frequencies above several hundred MHz is concentrated at the surface of a conductor. Therefore, RF impedance exhibits greater sensitivity compared to DC resistance in detecting early stages of interconnect degradation and provides a means to prevent and predict an important cause of electronics failures. This research identifies the applicability of RF impedance as a means of a failure precursor that allows for prognostics on interconnect degradation based on electrical measurement. It also compares the ability of RF impedance with that of DC resistance to detect early stages of interconnect degradation, and to predict the remaining life of an interconnect. To this end, RF impedance and DC resistance of a test circuit were simultaneously monitored during interconnect stress testing. The test vehicle included an impedance-controlled circuit board on which a surface mount component was soldered using two solder joints at the end terminations. During stress testing, the RF impedance exhibited a gradual non-linear increase in response to the early stages of solder joint cracking while the DC resistance remained constant. The gradual increase in RF impedance was trended using prognostic algorithms in order to predict the time to failure of solder joints. This prognostic approach successfully predicted solder joint remaining life with a prediction error of less than 3%. Furthermore, it was demonstrated both theoretically and experimentally that the RF impedance analysis was able to distinguish between two competing interconnect failure mechanisms: solder joint cracking and pad cratering. These results indicate that RF impedance provides reliable interconnect failure precursors that can be used to predict interconnect failures. Since the performance of high speed devices is adversely affected by early stages of interconnect degradation, RF impedance analysis has the potential to provide improved reliability assessment for these devices, as well as accurate failure prediction for current and future electronics.Item Electromagnetic Interference Reduction using Electromagnetic Bandgap Structures in Packages, Enclosures, Cavities, and Antennas(2007-11-26) Mohajer Iravani, Baharak; Ramahi, Omar M.; Granatstein, Victor L.; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Electromagnetic interference (EMI) is a source of noise problems in electronic devices. The EMI is attributed to coupling between sources of radiation and components placed in the same media such as package or chassis. This coupling can be either through conducting currents or through radiation. The radiation of electromagnetic (EM) fields is supported by surface currents. Thus, minimizing these surface currents is considered a major and critical step to suppress EMI. In this work, we present novel strategies to confine surface currents in different applications including packages, enclosures, cavities, and antennas. The efficiency of present methods of EM noise suppression is limited due to different drawbacks. For example, the traditional use of lossy materials and absorbers suffers from considerable disadvantages including mechanical and thermal reliability leading to limited life time, cost, volume, and weight. In this work, we consider the use of Electromagnetic Band Gap (EBG) structures. These structures are suitable for suppressing surface currents within a frequency band denoted as the bandgap. Their design is straight forward, they are inexpensive to implement, and they do not suffer from the limitations of the previous methods. A new method of EM noise suppression in enclosures and cavity-backed antennas using mushroom-type EBG structures is introduced. The effectiveness of the EBG as an EMI suppresser is demonstrated using numerical simulations and experimental measurements. To allow integration of EBGs in printed circuit boards and packages, novel miniaturized simple planar EBG structures based on use of high-k dielectric material (r > 100) are proposed. The design consists of meander lines and patches. The inductive meander lines serve to provide current continuity bridges between the capacitive patches. The high-k dielectric material increases the effective capacitive load substantially in comparison to commonly used material with much lower dielectric constant. Meander lines can increase the effective inductive load which pushes down the lower edge of bandgap, thus resulting in a wider bandgap. Simulation results are included to show that the proposed EBG structures provide very wide bandgap (~10GHz) covering the multiple harmonics of of currently available microprocessors and its harmonics. To speed up the design procedure, a model based on combination of lumped elements and transmission lines is proposed. The derived model predicts accurately the starting edge of bandgap. This result is verified with full-wave analysis. Finally, another novel compact wide band mushroom-type EBG structure using magneto-dielectric materials is designed. Numerical simulations show that the proposed EBG structure provides in-phase reflection bandgap which is several times greater than the one obtained from a conventional EBG operating at the same frequency while its cell size is smaller. This type of EBG structure can be used efficiently as a ground plane for low-profile wideband antennas.