UMD Theses and Dissertations
Permanent URI for this collectionhttp://hdl.handle.net/1903/3
New submissions to the thesis/dissertation collections are added automatically as they are received from the Graduate School. Currently, the Graduate School deposits all theses and dissertations from a given semester after the official graduation date. This means that there may be up to a 4 month delay in the appearance of a given thesis/dissertation in DRUM.
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Item INTEGRATED MODELING OF RELIABILITY AND PERFORMANCE OF 4H-SILICON CARBIDE POWER MOSFETS USING ATOMISTIC AND DEVICE SIMULATIONS(2015) Perinthatta Ettisserry, Devanarayanan; Goldsman, Neil; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)4H-Silicon Carbide (4H-SiC) power MOSFET is a promising technology for future high-temperature and high-power electronics. However, poor device reliability and performance, that stem from the inferior quality of 4H-SiC/SiO2 interface, have hindered its development. This dissertation investigates the role of interfacial and near-interfacial atomic defects as the root cause of these key concerns. Additionally, it explores device processing strategies for mitigating reliability-limiting defects. In order to understand the atomic nature of material defects, and their manifestations in electrical measurements, this work employs an integrated modeling approach together with experiments. Here, the electronic and structural properties of defects are analyzed using first-principles hybrid Density Functional Theory (DFT). The insights from first-principles calculations are integrated with conventional physics-based modeling techniques like Drift-Diffusion and Rate equation simulations to model various device characteristics. Subsequently, the atomic-level models are validated by comparison with experiments. From device reliability perspective, this dissertation models the time-dependent worsening of threshold voltage (Vth) instability in 4H-SiC MOSFETs operated under High-Temperature and Gate-Bias (HTGB) conditions. It proposes a DFT-based oxygen-vacancy hole trap activation model, where certain originally ‘electrically inactive’ oxygen vacancies are structurally transformed under HTGB stress to form electrically ‘active’ switching oxide hole traps. The transients of this atomistic process were simulated with inputs from DFT. The calculated time-evolution of the buildup of positively charged vacancies correlated well with the experimentally measured time-dependence of HTGB-induced Vth instability. Moreover, this work designates near-interfacial single carbon interstitial defect in SiO2 as an additional switching oxide hole trap that could cause room-temperature Vth instability. This work employs DFT-based molecular dynamics to develop device processing strategies that could mitigate reliability-limiting defects in 4H-SiC MOSFETs. It identifies Fluorine treatment to be effective in neutralizing oxygen vacancy and carbon-related hole traps, unlike molecular hydrogen. Similarly, Nitric Oxide passivation is found to eliminate carbon-related defects. From device performance perspective, this dissertation proposes a methodology to identify and quantify channel mobility-limiting interfacial defects by integrating Drift-Diffusion simulations of 4H-SiC power MOSFET with DFT. It identifies the density of interface trap spectrum to be composed of three atomically distinct defects, one of which is potentially carbon di-interstitial defect.Item Cause and Effect of Threshold-Voltage Instability on the Reliability of Silicon-Carbide MOSFETs(2011) Lelis, Aivars J.; Goldsman, Neil; Reliability Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)A significant instability of the threshold voltage (VT) in silicon carbide (SiC) MOSFETs in response to gate-bias and ON-state current stressing was discovered and examined as a function of bias, temperature, and time. It was determined that the likely mechanism causing this effect is the charging and discharging of gate-oxide traps, located close to the interface of the SiC conducting channel, via a direct tunneling mechanism. High-temperature reverse-bias induced leakage current in the OFF-state was identified as a potential failure mode. A simultaneous two-way tunneling model was developed, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. The simulations successfully matched experimental results, both with respect to measurement time and to bias-stress time as a function of gate bias. Experimental results were presented, showing that the VT instability increases with both increasing gate-bias-stress time and bias-stress magnitude. The measurement conditions, including gate-ramp speed and direction, were shown to have a significant influence on the measured result, with a 20-μs measurement revealing instabilities three times greater than those at standard 1-s measurement speeds, whereas 1-ks measurements showed shifts only half as large. High-temperature bias stressing was found to cause even more significant increases in the VT instability. ON-state current stressing was found to also increase the VT instability, due to self-heating effects. VT shifts as large as 2 V were reported, with the number of calculated oxide traps switching charge state varying between 1×1011 and 8×1011 cm–2, depending on processing, stress, and measurement conditions. The standard post-oxidation NO anneal was shown to reduce the number of active oxide traps by about 70 percent. The dominant oxide trap was identified as an E-prime-center type defect—a weak Si-Si bond due to an oxygen vacancy which has been broken during processing or subsequent device stressing. The large increase in bias-stress induced VT instability at temperatures above 100 °C was explained by an increase in the number of active E-prime-center type defects. Existing reliability qualification standards based on silicon device technology are inadequate for SiC MOSFETs and need to be revised, with particular attention paid to the measurement conditions.