Modelling and Measurement of Reciprocal Quantum Logic Circuits

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dc.contributor.advisorWellstood, Fredericken_US
dc.contributor.authorLuo, Henryen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2021-09-16T05:38:41Z
dc.date.available2021-09-16T05:38:41Z
dc.date.issued2021en_US
dc.description.abstractThis dissertation presents work on three aspects of Reciprocal Quantum Logic (RQL) circuits: devising accurate inductance models of Nb wires, analyzing, and measuring RQL logic gates, and mitigating the effects of parasitic coupling in RQL circuits. These separate aspects are all important to verify or improve the operating margins of RQL circuits. An inductance model for Nb wire routes based on electromagnetic simulation and measurement of inductance test circuits is described. The inductance test circuits are fabricated in the D-Wave Systems process. The inductance of straight segments, corners, and vias, and the mutual inductance between straight segments are modelled and measured. Measured data from 6 different releases and 8 wafers is presented. Proximity effects and wafer radial effects are discussed. Finally, a 2-material model for Nb wires is introduced and yields a good fit to the measured inductances. An RQL gates testbed chip was designed, fabricated, and tested. This chip was also fabricated in the D-wave Systems process. The measured gates included the buffer Josephson Transmission Line (JTL), delay JTL, and2, and or2 gates. Fifteen different design variations of each of these gates, which varied three inductors in the gate, are analyzed and shown to match well to simulation models. The variation in the upper operating limit or upper margin per design variation was roughly 3.5%, 5%, 7%, and 5% for the buffer JTL, delay JTL, and2, and or2, respectively. Tools were developed to account for and mitigate the effect of parasitic mutual coupling in RQL circuits. A back-annotation RQL tool (BART), to back-annotate parasitic mutual inductance, was developed for the extraction and simulation of small RQL designs. Using this tool on a 2x2 bit memory cell, the back-annotated simulation was able to explain measurements of the different operating regions for different test vectors. A methodology, bias point delta (BPD), for improving signal integrity of RQL circuits is also introduced. This methodology was applied to a 3,274 JJ design and the amount of coupled flux before and after routing improvements are compared. The work in this dissertation describes the development of models and tools that aid in the design of large RQL circuits, and it will serve as the groundwork for future research in RQL and potentially other Single Flux Quantum (SFQ) technologies.en_US
dc.identifierhttps://doi.org/10.13016/mrpe-2lkk
dc.identifier.urihttp://hdl.handle.net/1903/27757
dc.language.isoenen_US
dc.subject.pqcontrolledElectrical engineeringen_US
dc.subject.pqcontrolledPhysicsen_US
dc.subject.pquncontrolledInductanceen_US
dc.subject.pquncontrolledNiobiumen_US
dc.subject.pquncontrolledReciprocal Quantum Logicen_US
dc.subject.pquncontrolledSFQen_US
dc.subject.pquncontrolledSuperconductivityen_US
dc.titleModelling and Measurement of Reciprocal Quantum Logic Circuitsen_US
dc.typeDissertationen_US

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