On-Chip Thermoelectric Cooling of Semiconductor Hot Spot

dc.contributor.advisorBar-Cohen, Avramen_US
dc.contributor.authorWang, Pengen_US
dc.contributor.departmentMechanical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2007-09-28T15:03:47Z
dc.date.available2007-09-28T15:03:47Z
dc.date.issued2007-08-28en_US
dc.description.abstractThe Moore's Law progression in semiconductor technology, including shrinking feature size, increasing transistor density, and faster circuit speeds, is leading to increasing total power dissipations and heat fluxes on silicon chip. Moreover, in recent years, increasing performance has resulted in greater non-uniformity of on-chip power dissipation, creating microscale hot spots that can significantly degrade the processor performance and reliability. Application of conventional thermal packaging technology, developed to provide uniform chip cooling, to such chip designs results in lower allowable chip power dissipation or overcooling of large areas of the chip. Consequently, novel thermoelectric cooler (TEC) has been proposed recently for on-chip hot spot cooling because of its unique ability to selectively cool down the localized microscale hot spot. In this dissertation the potential application of thermoelectric coolers to suppress on-chip hotspots is explored using analytical modeling, numerical simulation, and experimental techniques. Single-crystal silicon is proposed as a potential thermoelectric material due to its high Seebeck coefficient and its thermoelectric cooling performance is investigated using device-level analytical modeling. Integrated on silicon chip as an integral, on-chip thermoelectric cooler, silicon microcooler can effectively reduce the hotspot temperature and its effectiveness is investigated using analytical modeling and numerical simulation, and found to be dependent of doping concentration in silicon, electric contact resistance, hotspot size, hotspot heat flux, die thickness and microcooler size. The other novel on-chip hotspot cooling solution developed in this dissertation is to use a mini-contact enhanced TEC, where the mini-contact pad connects the silicon chip and the TEC to concentrate the thermoelectric cooling power onto a spot of top surface of the silicon chip and therefore significantly improve the hotspot cooling performance. Numerical simulation shows hotspot cooling is determined by thermal contact resistance, thermoelectric element thickness, chip thickness, etc. Package-level experiment demonstrates that spot cooling performance of such mini-contact enhanced TEC can be improved by about 100%.en_US
dc.format.extent12150015 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/7413
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Mechanicalen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledThermoelectricen_US
dc.subject.pquncontrolledmicrocooleren_US
dc.subject.pquncontrolledhot spoten_US
dc.subject.pquncontrolledcoolingen_US
dc.subject.pquncontrolledsilicon chipen_US
dc.subject.pquncontrolledthermal managementen_US
dc.subject.pquncontrolledelectronic packagingen_US
dc.titleOn-Chip Thermoelectric Cooling of Semiconductor Hot Spoten_US
dc.typeDissertationen_US
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