Algorithm-Based Low-Power Digital Signal Processing System Designs

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1995

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In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In order to meet the low-power/high-throughput constraint, the key issue is to ﲣompensate the increased delay so that the device can be operated at the slowest possible speed without affecting the system throughput rate.

In this dissertation, new algorithmic- level techniques for compensating the increased delays based on the multirate approach are proposed.

Given the digital signal processing (DSP) problems, we apply the multirate approach to reformulate the algorithms so that the desired outputs can be obtained from the decimated input sequences. Since the data rate in the resulting multirate architectures is M- times slower than the original data rate while maintaining the same throughput rate, the speed penalty caused by the low supply voltage is compensated at the algorithmic/architectural level.

This new low-power design technique is applied to several important DSP applications. The first one is a design methodology for the low- power design of FIR/IIR systems. By following the proposed design procedures, users can convert a speed-demanding system function into its equivalent multirate transfer function. This methodology provides a systematic way for VLSI designers to design low- power/high-speed filtering architectures at the algorithmic/architectural level.

The multirate approach is also applied to the low-power transform coding architecture design. The resulting time-recursive multirate transform architectures inherit all advantages of the existing time-recursive transform architectures such as local communication, regularity, modularity, and linear hardware complexity, but the speed for updating the transform coefficients becomes M-times slower.

The last application is a programmable video co-processor system architecture that is capable of performing FIR/IIR filtering, subband filtering, discrete orthogonal transforms (DT) and adaptive filtering for the host processor in video applications. The system can be easily reconfigurated to perform multirate FIR/IIR/DT operations. Hence, we can either double the processing speed on-the-fly, based on the same processing elements, or apply this feature to the low- power implementation of this co- processor.

The methodology and the applications presented in this dissertation constitute a design framework for achieving low-power consumption at the algorithmic/architectural level for DSP applications.

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