Parallel Algorithms for VLSI Layout.
| dc.contributor.author | JaJa, Joseph F. | en_US |
| dc.contributor.author | Krishnamurthy, Sridhar | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:43:48Z | |
| dc.date.available | 2007-05-23T09:43:48Z | |
| dc.date.issued | 1989 | en_US |
| dc.description.abstract | Efficient automatic layout tools are clearly essential for designing complex VLSI systems. Recent efforts have been directed toward developing parallel algorithms to handle the different subproblems involved in the layout phase. Some of these algorithms have been shown to offer significant speed-ups over the sequential ones. In this chapter, basic parallel techniques that have been found to be effective for handling problems arising in the layout phase are reviewed. In particular, parallel algorithms for problems arising in paffitioning, placement and routing are discussed. The algorithms used to handle these problems can be classified into two broad categories: iterative or direct. The iterative techniques such as simulated annealing and the Kernighan-Lin algorithm are very effective for partitioning and placment. The direct methods seem to be dominant in routing. These methods and some new methods are discussed in the general context of parallel processing. Efficient algorithms for the shared-memory model and for distributed-memory multiprocessors such as the hypercube are described. In addition, several special-purpose hardware for placement and routing are also outlined and their merits discussed. | en_US |
| dc.format.extent | 2108947 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/4897 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; TR 1989-51 | en_US |
| dc.title | Parallel Algorithms for VLSI Layout. | en_US |
| dc.type | Technical Report | en_US |
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