Mesh-of-Trees Interconnection Network for an Explicitly Multi-Threaded Parallel Computer Architecture

Simple item page
dc.contributor.advisorVishkin, Uzien_US
dc.contributor.authorBalkan, Aydin Osmanen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2008-08-07T05:40:34Z
dc.date.available2008-08-07T05:40:34Z
dc.date.issued2008-08-05en_US
dc.description.abstractAs the multiple-decade long increase in clock rates starts to slow down, main-stream general-purpose processors evolve towards single-chip parallel processing. On-chip interconnection networks are essential components of such machines, supporting the communication between processors and the memory system. This task is especially challenging for some easy-to-program parallel computers, which are designed with performance-demanding memory systems. This study proposes an interconnection network, with a novel implementation of the Mesh-of-Trees (MoT) topology. The MoT network is evaluated relative to metrics such as wire area complexity, total register count, bandwidth, network diameter, single switch delay, maximum throughput per area, trade-offs between throughput and latency, and post-layout performance. It is also compared with some other traditional network topologies, such as mesh, ring, hypercube, butterfly, fat trees, butterfly fat trees, and replicated butterfly networks. Concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area cost. The layout of MoT network is evaluated using standard cell design methodology. A prototype chip with 8-terminal MoT network was taped out at $90nm$ technology and tested. In the context of an easy-to-program single-chip parallel processor, MoT network is embedded in the eXplicit Multi-Threading (XMT) architecture, and evaluated by running parallel applications. In addition to the basic MoT architecture, a novel hybrid extension of MoT is proposed, which allows significant area savings with a small reduction in throughput.en_US
dc.format.extent1380159 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/8368
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pqcontrolledComputer Scienceen_US
dc.subject.pquncontrolledMultiprocessor interconnection networksen_US
dc.subject.pquncontrolledMultistage interconnection networksen_US
dc.subject.pquncontrolledMesh of treesen_US
dc.subject.pquncontrolledNetwork-on-Chip (NoC)en_US
dc.subject.pquncontrolledParallel processingen_US
dc.titleMesh-of-Trees Interconnection Network for an Explicitly Multi-Threaded Parallel Computer Architectureen_US
dc.typeDissertationen_US

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
umi-umd-5685.pdf
Size:
1.32 MB
Format:
Adobe Portable Document Format
Download

Collections

UMD Theses and Dissertations
Electrical & Computer Engineering Theses and Dissertations