LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS
| dc.contributor.advisor | Newcomb, Robert | en_US |
| dc.contributor.author | He, Xinhua | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2007-09-28T15:01:30Z | |
| dc.date.available | 2007-09-28T15:01:30Z | |
| dc.date.issued | 2007-08-03 | en_US |
| dc.description.abstract | The phase-locked loop (PLL) frequency synthesizer is a critical device of wireless transceivers. It works as a local oscillator (LO) for frequency translation and channel selection in the transceivers but suffers phase noise including reference spurs. In this dissertation for lowing phase noise and power consumption, efforts are placed on the new design of PLL components: VCOs, charge pumps and sigma delta modulators. Based on the analysis of the VCO phase noise generation mechanism and improving on the literature results, a design-oriented phase noise model for a complementary cross-coupled LC VCO is provided. The model reveals the relationship between the phase noise performance and circuit design parameters. Using this phase noise model, an optimized 2GHz low phase noise CMOS LC VCO is designed, simulated and fabricated. The theoretical analysis results are confirmed by the simulation and experimental results. With this VCO phase noise model, we also design a low phase noise, low gain wideband VCO with the typical VCO gain around 100MHz/V. Improving upon literature results, a complete quantitative analysis of reference spur is given in this dissertation. This leads to a design of a charge pump by using a negative feedback circuit and replica bias to reduce the current mismatch which causes the reference spur. In addition, low-impedance charge/discharge paths are provided to overcome the charge pump current glitches which also cause PLL spurs. With a large bit-width high order sigma delta modulator, the fractional-N PLL has fine frequency resolution and fast locking time. Based on an analysis of sigma delta modulator models introduced in this dissertation, a 3rd-order MASH 1-1-1 digital sigma delta modulator is designed. Pipelining techniques and true single phase clock (TSPC) techniques are used for saving power and area. Included is the design of a fully integrated 2.4GHz ยงยข fractional-N CMOS PLL frequency synthesizer. It takes advantage of a sigma delta modulator to get a very fine frequency resolution and a relatively large loop bandwidth. This frequency synthesizer is a 4th-order charge pump PLL with 26MHz reference frequency. The loop bandwidth is about 150KHz, while the whole PLL phase noise is about -120dBc/Hz at 1MHz frequency offset. | en_US |
| dc.format.extent | 2625049 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/7337 | |
| dc.language.iso | en_US | |
| dc.subject.pqcontrolled | Engineering, Electronics and Electrical | en_US |
| dc.title | LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS | en_US |
| dc.type | Dissertation | en_US |
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