Design, Implementation and Testing of an 8x8 DCT Chip
| dc.contributor.advisor | JaJa, J. | en_US |
| dc.contributor.author | Sachidanandan, S. | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:44:56Z | |
| dc.date.available | 2007-05-23T09:44:56Z | |
| dc.date.issued | 1989 | en_US |
| dc.description.abstract | An implementation of a fully pipelined bit serial architecture to compute the 2-D Discrete Cosine Tranform of an 8x8 element matrix is presented. The algorithm used requires the minimal number of multipliers to perform the computation. The basic hardware components required by our implementation are the one bit serial adder, one bit serial subtractor, one bit pipeline multiplier and the dynamic shift register. We use two's complement arithmetic. An internal precision of 18 bits is maintained throughout the chip. We have used the two phase non-overlapping clocking scheme. The basic architecture consists of an 1-D ROW DCT followed by a TRANSPOSE operation and another 1-D COLUMN DCT. All the components were custom designed and simulated at various levels. The chips were laid out using the layout editor MAGIC and were fabricated by MOSIS. The chips were tested using the IMS Logic Master. The results of the simulation and testing are also presented here. The throughput is very high and inputs can be processed successively with no delay and just two controls. The chip is designed to operate at clock speeds of 10Mhz or more. | en_US |
| dc.format.extent | 2842544 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/4952 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; MS 1989-5 | en_US |
| dc.subject | Systems Integration | en_US |
| dc.title | Design, Implementation and Testing of an 8x8 DCT Chip | en_US |
| dc.type | Thesis | en_US |
Files
Original bundle
1 - 1 of 1