PROTOTYPING THE SIMULATION OF A GATE LEVEL LOGIC APPLICATION PROGRAM INTERFACE (API) ON AN EXPLICIT-MULTI-THREADED (XMT) COMPUTER
| dc.contributor.advisor | Vishkin, Uzi | en_US |
| dc.contributor.author | gu, pei | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2005-08-03T15:15:19Z | |
| dc.date.available | 2005-08-03T15:15:19Z | |
| dc.date.issued | 2005-05-31 | en_US |
| dc.description.abstract | Explicit-multi-threading (XMT) is a parallel programming approach for exploiting on-chip parallelism. Its fine-grained SPMD programming model is suitable for many computing intensive applications. In this paper, we present a parallel gate level logic simulation algorithm and study its implementation on an XMT processor. The test results show that hundreds-fold speedup can be achieved. | en_US |
| dc.format.extent | 253717 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/2626 | |
| dc.language.iso | en_US | |
| dc.subject.pqcontrolled | Computer Science | en_US |
| dc.title | PROTOTYPING THE SIMULATION OF A GATE LEVEL LOGIC APPLICATION PROGRAM INTERFACE (API) ON AN EXPLICIT-MULTI-THREADED (XMT) COMPUTER | en_US |
| dc.type | Thesis | en_US |
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