XMT-M: A Scalable Decentralized Processor
| dc.contributor.author | Berkovich, Efraim | en_US |
| dc.contributor.author | Nuzman, Joseph | en_US |
| dc.contributor.author | Franklin, Manoj | en_US |
| dc.contributor.author | Jacob, Bruce | en_US |
| dc.contributor.author | Vishkin, Uzi | en_US |
| dc.date.accessioned | 2004-05-31T22:59:28Z | |
| dc.date.available | 2004-05-31T22:59:28Z | |
| dc.date.created | 1999-09 | en_US |
| dc.date.issued | 1999-10-09 | en_US |
| dc.description.abstract | A defining challenge for research in computer science and engineering has been the ongoing quest for reducing the completion time of a single computation task. Even outside the parallel processing communities, there is little doubt that the key to further progress in this quest is to do parallel processing of some kind. A recently proposed parallel processing framework that spans the entire spectrum from (parallel) algorithms to architecture to implementation is the explicit multi-threading (XMT) framework. This framework provides: (i) simple and natural parallel algorithms for essentially every general-purpose application, including notoriously difficult irregular integer applications, and (ii) a multi-threaded programming model for these algorithms which allows an ``independence-of-order'' semantics: every thread can proceed at its own speed, independent of other concurrent threads. To the extent possible, the XMT framework uses established ideas in parallel processing. This paper presents XMT-M, a microarchitecture implementation of the XMT model that is possible with current technology. XMT-M offers an engineering design point that addresses four concerns: buildability, programmability, performance, and scalability. The XMT-M hardware is geared to execute multiple threads in parallel on a single chip: relying on very few new gadgets, it can execute parallel threads without busy-waits! Existing code can be run on XMT-M as a single thread without any modifications, thereby providing backward compatibility for commercial acceptance. Simulation-based studies of XMT-M demonstrate considerable improvements in performance relative to the best serial processor even for small, and therefore practical, input sizes. (Also cross-referenced as UMIACS-TR-99-55) | en_US |
| dc.format.extent | 1319986 bytes | |
| dc.format.mimetype | application/postscript | |
| dc.identifier.uri | http://hdl.handle.net/1903/1030 | |
| dc.language.iso | en_US | |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_US |
| dc.relation.isAvailableAt | University of Maryland (College Park, Md.) | en_US |
| dc.relation.isAvailableAt | Tech Reports in Computer Science and Engineering | en_US |
| dc.relation.isAvailableAt | UMIACS Technical Reports | en_US |
| dc.relation.ispartofseries | UM Computer Science Department; CS-TR-4061 | en_US |
| dc.relation.ispartofseries | UMIACS; UMIACS-TR-99-55 | en_US |
| dc.title | XMT-M: A Scalable Decentralized Processor | en_US |
| dc.type | Technical Report | en_US |