Feasibility Study of Scaling an XMT Many-Core
| dc.contributor.author | O'Brien, Sean | |
| dc.contributor.author | Vishkin, Uzi | |
| dc.contributor.author | Edwards, James | |
| dc.contributor.author | Waks, Edo | |
| dc.contributor.author | Yang, Bao | |
| dc.date.accessioned | 2015-02-26T22:25:37Z | |
| dc.date.available | 2015-02-26T22:25:37Z | |
| dc.date.issued | 2015-01-19 | |
| dc.description.abstract | The reason for recent focus on communication avoidance is that high rates of data movement become infeasible due to excessive power dissipation. However, shifting the responsibility of minimizing data movement to the parallel algorithm designer comes at significant costs to programmer’s productivity, as well as: (i) reduced speedups and (ii) the risk of repelling application developers from adopting parallelism. The UMD Explicit Multi-Threading (XMT) framework has demonstrated advantages on ease of parallel programming through its support of PRAM-like programming, combined with strong, often unprecedented speedups. Such programming and speedups involve considerable data movement between processors and shared memory. Another reason that XMT is a good test case for a study of data movement is that XMT permits isolation and direct study of most of its data movement (and its power dissipation). Our new results demonstrate that an XMT single-chip many-core processor with tens of thousands of cores and a high throughput network on chip is thermally feasible, though at some cost. This leads to a perhaps game-changing outcome: instead of imposing upfront strict restrictions on data movement, as advocated in a recent report from the National Academies, opt for due diligence that accounts for the full impact on cost. For example, does the increased cost due to communication avoidance (including programmer’s productivity, reduced speedups and desertion risk) indeed offset the cost of the solution we present? More specifically, we investigate in this paper the design of an XMT many-core for 3D VLSI with microfluidic cooling. We used state-of-the-art simulation tools to model the power and thermal properties of such an architecture with 8k to 64k lightweight cores, requiring between 2 and 8 silicon layers. Inter-chip communication using silicon compatible photonics is also considered. We found that, with the use of microfluidic cooling, power dissipation becomes a cost issue rather than a feasibility constraint. Robustness of the results is also discussed. | en_US |
| dc.description.sponsorship | DARPA, NSF, NIH | en_US |
| dc.identifier | https://doi.org/10.13016/M2XK7J | |
| dc.identifier.uri | http://hdl.handle.net/1903/16316 | |
| dc.language.iso | en_US | en_US |
| dc.relation.isAvailableAt | College of Computer, Mathematical & Natural Sciences | en_us |
| dc.relation.isAvailableAt | Computer Science | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.subject | data movement | en_US |
| dc.subject | parallel algorithms | en_US |
| dc.subject | PRAM | en_US |
| dc.subject | parallel architecture | en_US |
| dc.subject | many-core | en_US |
| dc.subject | 3D VLSI | en_US |
| dc.subject | microfluidic cooling | en_US |
| dc.subject | silicon photonics | en_US |
| dc.title | Feasibility Study of Scaling an XMT Many-Core | en_US |
| dc.type | Other | en_US |