Characterization of Electrically Active Defects in Advanced Gate Dielectrics

Abstract

As the gate oxide thickness of the metal-oxide-semiconductor (MOS) Field Effect Transistor (FET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding device reliability. Substitute dielectrics with high dielectric constant (high-k) have been proposed to replace traditional SiO2 to reduce the leakage current in future devices. However, these high-k dielectrics also have reliability issues due to the large amount of intrinsic trapping centers.

In this work, electrically active defects generated during electrical stress of ultrathin SiO2 dielectrics are characterized and studied. The mechanism of oxide breakdown is studied by investigating the contributions of hot holes to device time-to-breakdown (tbd). The proper extrapolation of tbd from accelerated testing conditions to normal device operating conditions is also studied. The factors that affect this extrapolation are discussed. Another important device reliability parameter, threshold voltage shift (Vth), is also investigated in this work. The dominant mechanisms causing this shift is studied using both simulation and experimental results.

The current primary reliability issue with high-k dielectrics is the large amount of intrinsic traps located in the dielectric stack. Therefore, the electrical characterization of high-k dielectrics in this work is focused on these initial as-fabricated trapping centers. A methodology based on 2-level charge pumping (CP) measurements at different frequencies is used to study the spatial profile of these trapping centers. The correlation between device fabrication data and measurement results indicates this methodology is accurate and reliable.