A pll based frequency synthesizer in 0.13 um sige bicmos for mb-ofdm uwb systems

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dc.contributor.advisorPeckerar, Martinen_US
dc.contributor.authorChiang, Hsin-Cheen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2007-09-28T15:02:24Z
dc.date.available2007-09-28T15:02:24Z
dc.date.issued2007-08-13en_US
dc.description.abstractWith the growing demand for high-speed and high-quality short-range communication, multi-band orthogonal frequency division multiplexing ultra-wide band (MB-OFDM UWB) systems have recently garnered considerable interest in industry and in academia. To achieve a low-cost solution, highly integrated transceivers with small die area and minimum power consumption are required. The key building block of the transceiver is the frequency synthesizer. A frequency synthesizer comprised of two PLLs and one multiplexer is presented in this thesis. Ring oscillators are adopted for PLL implementation in order to drastically reduce the die area of the frequency synthesizer. The poor spectral purity appearing in the frequency synthesizers involving mixers is greatly improved in this design. Based on the specifications derived from application standards, a design methodology is presented to obtain the parameters of building blocks. As well, the simulation results are provided to verify the performance of proposed design.en_US
dc.format.extent1183515 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/7372
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledpllen_US
dc.subject.pquncontrolleduwben_US
dc.subject.pquncontrolledrf transcevieren_US
dc.titleA pll based frequency synthesizer in 0.13 um sige bicmos for mb-ofdm uwb systemsen_US
dc.typeThesisen_US

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