Thermal Modeling and Analysis of Three Dimensional (3D) Chip Stacks

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dc.contributor.advisorBar-Cohen, Avramen_US
dc.contributor.advisorKim, Junghoen_US
dc.contributor.authorBachmann, Christopheren_US
dc.contributor.departmentMechanical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2007-09-28T15:03:56Z
dc.date.available2007-09-28T15:03:56Z
dc.date.issued2007-09-11en_US
dc.description.abstractThree-dimensional (3D) chip architectures have garnered much research interest because of their potential to alleviate the interconnect delay bottleneck that is expected to limit the traditional progression of Moore's law through device scaling in planar chips. While the benefits of 3D chip integration are clear, there are several obstacles to its broader implementation. In particular, the issue of power dissipation is a major challenge to the development of high performance 3D chip stacks. The well-documented difficulties in cooling future 2D chips will only be exacerbated by 3D architectures in which volumetric power density is increased and non-uniform power dissipation is more severe. This thesis focuses on three relevant topics in the cooling of 3D chip stacks: 1) the determination of effective thermal properties for use in compact thermal models, 2) single phase internal liquid cooling, and 3) hot spot remediation with anisotropic thermal interface materials.en_US
dc.format.extent3516237 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/7419
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Mechanicalen_US
dc.subject.pqcontrolledEngineering, Mechanicalen_US
dc.titleThermal Modeling and Analysis of Three Dimensional (3D) Chip Stacksen_US
dc.typeThesisen_US

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