The Design and the Testing of a 64-Processor Array
| dc.contributor.advisor | JaJa, J. | en_US |
| dc.contributor.author | Wang, H. | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:42:53Z | |
| dc.date.available | 2007-05-23T09:42:53Z | |
| dc.date.issued | 1988 | en_US |
| dc.description.abstract | Array architectures based on the VLSI technology allow the processing speed to increase by several orders of magnitude. While VLSI holds the promise of high parallelism by offering almost unlimited hardware at very low cost, there are several inherent constraints with respect to communication, design complexity, testability, etc. In this paper, we are concerned with design and testing of such an architecture. An array- processor chip consisting of 8x8 processing elements (PEs) each with 512 bits of memory was fully designed and fabricated using 2m CMOS technology. One of the novel features of this design is the capability to load data fast into all the PEs simultaneously. Extensive simulations were carried out on this design. This general purpose parallel processor chip was tested using the test workstation IMS-VS2000. An application board was also built by using the Macintosh II as the host controller. | en_US |
| dc.format.extent | 3602125 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/4848 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; MS 1988-4 | en_US |
| dc.subject | Chemical Process Systems | en_US |
| dc.title | The Design and the Testing of a 64-Processor Array | en_US |
| dc.type | Thesis | en_US |
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