A Fully Parallel and Pipelined Systolic Array for MVDR Beamforming
dc.contributor.author | Tang, C.F.T. | en_US |
dc.contributor.author | Liu, K.J. Ray | en_US |
dc.contributor.department | ISR | en_US |
dc.date.accessioned | 2007-05-23T09:48:46Z | |
dc.date.available | 2007-05-23T09:48:46Z | |
dc.date.issued | 1991 | en_US |
dc.description.abstract | A fully-pipelined systolic array for computing the minimum variance distortionless response (MVDR) was first proposed by McWhirter and Shepherd. The fundamental concept is to fit the MVDR beamforming to the non-contrainted recursive least-squares (RLS) minimization. Until now, their systolic array processor is well-recognized as the most efficient design for MVDR beamforming. In this paper, we first point out the mistake by relating the MVRD beamforming and RLS minimization and then propose a new algorithm for the MVDR beamforming. Moreover, a fully parallel and pipelined systolic array for the newly proposed algorithm is presented and the square-root free implementation is also considered. | en_US |
dc.format.extent | 786338 bytes | |
dc.format.mimetype | application/pdf | |
dc.identifier.uri | http://hdl.handle.net/1903/5137 | |
dc.language.iso | en_US | en_US |
dc.relation.ispartofseries | ISR; TR 1991-89 | en_US |
dc.subject | signal processing | en_US |
dc.subject | parallel architectures | en_US |
dc.subject | VLSI architectures | en_US |
dc.subject | Systems Integration | en_US |
dc.title | A Fully Parallel and Pipelined Systolic Array for MVDR Beamforming | en_US |
dc.type | Technical Report | en_US |
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