A Fully Parallel and Pipelined Systolic Array for MVDR Beamforming

dc.contributor.authorTang, C.F.T.en_US
dc.contributor.authorLiu, K.J. Rayen_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:48:46Z
dc.date.available2007-05-23T09:48:46Z
dc.date.issued1991en_US
dc.description.abstractA fully-pipelined systolic array for computing the minimum variance distortionless response (MVDR) was first proposed by McWhirter and Shepherd. The fundamental concept is to fit the MVDR beamforming to the non-contrainted recursive least-squares (RLS) minimization. Until now, their systolic array processor is well-recognized as the most efficient design for MVDR beamforming. In this paper, we first point out the mistake by relating the MVRD beamforming and RLS minimization and then propose a new algorithm for the MVDR beamforming. Moreover, a fully parallel and pipelined systolic array for the newly proposed algorithm is presented and the square-root free implementation is also considered.en_US
dc.format.extent786338 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5137
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1991-89en_US
dc.subjectsignal processingen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleA Fully Parallel and Pipelined Systolic Array for MVDR Beamformingen_US
dc.typeTechnical Reporten_US

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