VLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Applications

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dc.contributor.authorSrinivasan, V.en_US
dc.contributor.authorLiu, K.J. Rayen_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:56:59Z
dc.date.available2007-05-23T09:56:59Z
dc.date.issued1994en_US
dc.description.abstractIn this paper we present a full-customer VLSI design of high- speed 2-D DCT/IDCT Processor based on the new class of time- recursive algorithms and architectures which has never been implemented to prove its performance. We show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. Our design of the 8 x 8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2 CMOS technology. In comparison to the existing designs, our approach offers many advantages that can be further explored for even higher performance.en_US
dc.format.extent1742553 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5534
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1994-60en_US
dc.subjectsignal processingen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integration Methodologyen_US
dc.titleVLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Applicationsen_US
dc.typeTechnical Reporten_US

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