Low Frequency Noise in CMOS transistors

Thumbnail Image


Publication or External Link






The minimum measurable signal strength of an electronic system is limited by noise. With the advent of very large scale integrated (VLSI) systems, low power designs are achieved by reducing the supply voltage and the drive current. This reduces the dynamic range of the system. As the signal in an amplifier system is usually set to be a significant fraction of the dynamic range, all other factors being equal, reduction in dynamic range leads to a degradation of the signal to noise ratio (SNR). This thesis addresses this issue in low power design.

Focus is given to low frequency (< 1 kHz) noise. This frequency range is dominated by flicker noise, also referred to as pink or 1/f noise. Most biomedical and audio signals lie in this low frequency domain. For example, electrocardiograms (ECGs) record signals which are < 50 Hz. Audio signals have a large portion of signals that lie in the low frequency bandwidth. The focus here is on low-frequency performance of CMOS transistors. This represents a significant challenge in detection as noise in solid state devices tends to increase with decreases in frequency. That is, it becomes ``pink," weighted to the low frequency spectral range. Usually, we find that noise power changes reciprocally with frequency as we reach the kilohertz frequency range.

While there has been no single, definitive theory of pink noise, system design principles can be formulated to minimize the impact of this noise. There are two factors to consider here. First, the pink noise process appears to be related to interaction with the defect structure of the solid through which charge is transported. As the number of defects is finite, there is a limit to the number of charges that can interact with this defect population. Thus, there is a limit on the amount of fluctuation in this interaction ``current." This limit depends on the number of defects present in the solid through which transport occurs. It also depends on the number of charges transported. Thus, the trivial and often cited optimization principle demanding a reduced solid defect density presents itself.

This leads to a second, less obvious principle of optimization. If the number of transported charges is large, and the trap defect parameters (number density, cross-section, trap lifetime, etc.) does not depend on total current passed, it is possible to overcome" the defect-related noise. This is done by increasing the bias current. For fixed defect density, increased bias current will saturate" the 1/f-noise fluctuation at some level resulting in an increase in SNR.

Large current leads to large power dissipation, an undesirable side-effect of saturating the 1/f-noise current. This problem of SNR and power optimization has been addressed in this work.

The main contribution of the work is development of an analog design methodology utilizing saturation effect to improve system SNR through bias optimization. Flicker noise measurement was carried out for the low frequency region in 0.5um and 130 nm CMOS process and SNR studied under different gate bias voltages. We further investigated the impact of size variation, radiation stress and hot electron injection on the optimal bias point of the device. In addition, low temperature noise spectroscopy was conducted to study the noise behavior. Double channel method was used which enabled measurement of pink noise at very low gate biases. The work investigates signal, noise and power in deep-subthreshold region for the first time.