Hybrid-PGAS Memory Hierarchy for Next Generation HPC Systems

dc.contributor.advisorHollingsworth, Jeffrey Ken_US
dc.contributor.authorJohnson, Richard Bradforden_US
dc.contributor.departmentComputer Scienceen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2024-09-23T06:12:39Z
dc.date.available2024-09-23T06:12:39Z
dc.date.issued2024en_US
dc.description.abstractDemands on computational performance, power efficiency, data transfer, resource capacity, and resilience for next generation high performance computing (HPC) systems present a new host of challenges. There is a growing disparity between computational performance vs. network and storage device throughput and among the energy costs of computational, memory, and communication operations. Chapel is a powerful, high-level, parallel, PGAS language designed to streamline development by addressing code complexities and uses a shared memory model for handling large, distributed memory systems. I extended the capabilities of Chapel by providing support of persistent memory with intrinsic and programmatic features for HPC systems. In my approach I explored the efficacy of persistent memory in a hybrid-PGAS environment through latency hiding analysis via cache monitoring, identification and mitigation of performance bottlenecks via data-centric analysis, and hardware profiling to assess performance cost vs. benefits and energy footprint. To manage persistency and ensure resiliency I developed a transaction system with ACID properties that supports hybrid-PGAS virtual addressing and distributed checkpoint and recovery system.en_US
dc.identifierhttps://doi.org/10.13016/u1yj-wmmc
dc.identifier.urihttp://hdl.handle.net/1903/33407
dc.language.isoenen_US
dc.subject.pqcontrolledComputer scienceen_US
dc.subject.pquncontrolledChapel languageen_US
dc.subject.pquncontrolledemerging technologiesen_US
dc.subject.pquncontrolledhigh performance computingen_US
dc.subject.pquncontrollednext generation computingen_US
dc.subject.pquncontrollednon-volatile memoryen_US
dc.subject.pquncontrolledparallel and distributed computingen_US
dc.titleHybrid-PGAS Memory Hierarchy for Next Generation HPC Systemsen_US
dc.typeDissertationen_US

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