Hybrid-PGAS Memory Hierarchy for Next Generation HPC Systems
dc.contributor.advisor | Hollingsworth, Jeffrey K | en_US |
dc.contributor.author | Johnson, Richard Bradford | en_US |
dc.contributor.department | Computer Science | en_US |
dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
dc.date.accessioned | 2024-09-23T06:12:39Z | |
dc.date.available | 2024-09-23T06:12:39Z | |
dc.date.issued | 2024 | en_US |
dc.description.abstract | Demands on computational performance, power efficiency, data transfer, resource capacity, and resilience for next generation high performance computing (HPC) systems present a new host of challenges. There is a growing disparity between computational performance vs. network and storage device throughput and among the energy costs of computational, memory, and communication operations. Chapel is a powerful, high-level, parallel, PGAS language designed to streamline development by addressing code complexities and uses a shared memory model for handling large, distributed memory systems. I extended the capabilities of Chapel by providing support of persistent memory with intrinsic and programmatic features for HPC systems. In my approach I explored the efficacy of persistent memory in a hybrid-PGAS environment through latency hiding analysis via cache monitoring, identification and mitigation of performance bottlenecks via data-centric analysis, and hardware profiling to assess performance cost vs. benefits and energy footprint. To manage persistency and ensure resiliency I developed a transaction system with ACID properties that supports hybrid-PGAS virtual addressing and distributed checkpoint and recovery system. | en_US |
dc.identifier | https://doi.org/10.13016/u1yj-wmmc | |
dc.identifier.uri | http://hdl.handle.net/1903/33407 | |
dc.language.iso | en | en_US |
dc.subject.pqcontrolled | Computer science | en_US |
dc.subject.pquncontrolled | Chapel language | en_US |
dc.subject.pquncontrolled | emerging technologies | en_US |
dc.subject.pquncontrolled | high performance computing | en_US |
dc.subject.pquncontrolled | next generation computing | en_US |
dc.subject.pquncontrolled | non-volatile memory | en_US |
dc.subject.pquncontrolled | parallel and distributed computing | en_US |
dc.title | Hybrid-PGAS Memory Hierarchy for Next Generation HPC Systems | en_US |
dc.type | Dissertation | en_US |
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