We present detailed physics based numerical models for characterizing 4H-Silicon Carbide lateral MOSFETs and vertical power DMOSFETs for high temperature, high field, DC, AC and transient switching operating conditions. A complete 2-D Drift-Diffusion based device simulator has been developed specifically for SiC MOSFETs, to evaluate device performance in a variety of operating scenarios, and to extract relevant physical parameters.

We have developed and implemented room and high temperature mobility models for bulk phonon and impurity scattering, surface phonon scattering, Coulomb scattering from interface traps, and surface roughness scattering. High temperature models for interface trap density of states and occupation probability of interface traps are also implemented. By rigorous comparison of simulated I-V characteristics to experimental data at high temperatures, physical parameters like interface trap density of states, surface step height, saturation velocity, etc. have been extracted. Insight into relative importance of scattering mechanisms influencing transport in SiC MOSFETs has been provided. We show that the strongest contribution to low current in SiC MOSFETs is from the loss of mobile inversion charge due to large amount of trapping at the interface, and due to very low surface mobility arising due to a rough SiC-SiO₂ interface. We show that surface roughness scattering dominates at high gate biases and is the most important scattering mechanism in 4H-SiC MOSFETs.

Switching characteristics of SiC lateral MOSFETs have been modeled and simulated using our custom device simulator. A comprehensive generation-recombination model for interaction between inversion layer electrons and interface traps has been developed. Using this model, we have modeled the time-dependent occupation of interface traps spread inside the SiC bandgap. We have measured the transient characteristics of these devices, and compare our simulation to experiment and have extracted capture cross-sections of interface traps. Using the coupled experiment and modeling approach, we are able to distinguish between fast interface traps and slow oxide traps, and explain how they contribute to threshold voltage instability.

High power 4H-SiC DMOSFET operation in the ON and the OFF states has also been analyzed. We show that in current generation SiC DMOSFETs, the ON resistance is dominated by the channel resistance instead of the drift-layer resistance. This makes the design of SiC DMOSFETs far from ideal. OFF state blocking capability and breakdown due to impact ionization of the DMOSFETs are also modeled and simulated. We show that the 4H-SiC DMOSFETs have excellent leakage characteristics and can support extremely high OFF state drain voltages.