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Analysis and Design of High-Speed A/D Converters in SiGe Technology

dc.contributor.advisorPeckerar, Martinen_US
dc.contributor.authorChen, Po-Hsinen_US
dc.date.accessioned2008-04-22T16:03:33Z
dc.date.available2008-04-22T16:03:33Z
dc.date.issued2007-11-21en_US
dc.identifier.urihttp://hdl.handle.net/1903/7653
dc.description.abstractMixed-signal systems play a key role in modern communications and electronics. The quality of A/D and D/A conversions deeply affects what we see and what we hear in the real world video and radio. This dissertation deals with high-speed ADCs: a 5-bit 500-MSPS ADC and an 8-bit 2-GSPS ADC. These units can be applied in flat panel display, image enhancement and in high-speed data link. To achieve the state-of-the-art performance, we employed a 0.13-μm/2.5-V 210-GHz (unity-gain frequency) BiCMOS SiGe process for all the implementations. The circuit building blocks, such as the Track-and-Hold circuit (T/H) and the comparator, required by an ADC not only benefit from SiGe's superior ultra-high frequency properties but also by its power drive capability. The T/H described here achieved a dynamic performance of 8-bit accuracy at 2-GHz Nyquist rate with an input full scale range of 1 Vp-p. The T/H consumed 13 mW of power. The unique 4-in/2-out comparator was made of fully differential emitter couple pairs in order to operate at such a high frequency. Cascaded cross-coupled amplifier core was employed to reduce Miller effect and to avoid collector-emitter breakdown of the HBTs. We utilized the comparator interpolation technique between the preamplifer stages and the latches to reduce the total power dissipated by the comparator array. In addition, we developed an innovative D/A conversion and analog subtraction approach necessary for two-step conversion by using a bipolar pre-distortion technique. This innovation enabled us to decrease the design complexity in the subranging process of a two-step ADC. The 5-bit interpolating ADC operated at 2-GSPS achieved a differential nonlinearity (DNL) of 0.114 LSB and an integral nonlinearity (INL) of 0.076 LSB. The effective number of bits (ENOBs) are 4.3 bits at low frequency and 4.1 bits near Nyquist rate. The power dissipation was reduced more than half to 66.14 mW, with comparator interpolation. The 8-bit two-step interpolating ADC operated at 500-MSPS. It achieved a DNL of 0.33 LSB and an INL of 0.40 LSB with a power consumption of 172 mW. The ENOBs are 7.5 bits at low frequency and 6.9 bits near Nyquist rate.en_US
dc.format.extent1882408 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.titleAnalysis and Design of High-Speed A/D Converters in SiGe Technologyen_US
dc.typeDissertationen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.contributor.departmentElectrical Engineeringen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledADCen_US
dc.subject.pquncontrolledSiGeen_US
dc.subject.pquncontrolledBiCMOSen_US
dc.subject.pquncontrolledhigh-speeden_US
dc.subject.pquncontrolledtrack-and-holden_US
dc.subject.pquncontrolledcomparatoren_US
dc.subject.pquncontrolledDACen_US
dc.subject.pquncontrolledsubtractoren_US
dc.subject.pquncontrolledsubrangingen_US


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