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Substrate interconnect technologies for 3-DMEMS packaging

dc.contributor.authorMorgan, Brianen_US
dc.contributor.authorHuab, Xuefengen_US
dc.contributor.authorIguchi, Tomohiroen_US
dc.contributor.authorTomiokaf, Taizoen_US
dc.contributor.authorOehrlein, Gottlieb S.en_US
dc.contributor.authorGhodssi, Rezaen_US
dc.date.accessioned2007-05-23T10:17:56Z
dc.date.available2007-05-23T10:17:56Z
dc.date.issued2005en_US
dc.identifier.urihttp://hdl.handle.net/1903/6557
dc.description.abstractWe report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at d on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 lm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.en_US
dc.format.extent717380 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 2005-94en_US
dc.titleSubstrate interconnect technologies for 3-DMEMS packagingen_US
dc.typeTechnical Reporten_US
dc.contributor.departmentISRen_US


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