Bats are known for their ability to pursue a goal while avoiding obstacles in a cluttered environment using ultrasonic echolocation. This dissertation explores two neuromorphic mechanisms involved in such a task: a conductance-based neuron circuit for azimuthal echolocation whose dynamic range can be expanded by power-law compression, and a sonar-based obstacle avoidance algorithm with its spike-latency model implementation. Bats and other mammals use interaural level differences (ILD) to estimate the direction of high-frequency sounds. To compute the ILD of a sound, independent of overall loudness, excitatory and inhibitory synaptic conductances (encoding the left and right amplitudes) are hypothesized to compete in the neurons of the lateral superior olive. Interestingly, this neural model can also accept power-law compressed amplitudes that can allow a much larger range of input signal levels, a common limitation in neural coding. This dissertation demonstrates the use of square-root and cube-root compression with a neuromorphic VLSI neuron to expand the range of distances over which ILD can be used to estimate echo direction in a sonar system based on echolocating bats. However, many questions remain regarding how to achieve the rapid control of a sonar-guided vehicle to pursue a goal while avoiding obstacles. Taking into account the limited field-of-view of practical sonar systems and vehicle kinematics, we propose an obstacle avoidance algorithm that maps the 2-D sensory space into a 1-D motor space and evaluates motor actions while combining obstacles and goal information. A winner-take-all (WTA) mechanism is used to select the final steering action. To avoid unnecessary scanning of the environment, an attentional system is proposed to control the directions of sonar pings for efficient, task-driven, sensory data collection. A mobile robot driven by the proposed algorithm was capable of navigating through a cluttered environment using a realistic sonar system. The algorithm was tested on a mobile robot, and it is implemented on a neural model using spike-timing representations, a spike-latency memory, and a “race-to-first-spike” WTA circuit. This dissertation also proposed a CMOS floating-gate circuit for artificial neural network synapse memories that can achieve a fixed rate of weight increase (adding vectors) or proportional decay (normalization) on the synaptic weight.