Reliability of Copper-Filled Stacked Microvias in High Density Interconnect Circuit Boards

Abstract

The electronics industry strives to produce affordable, lightweight, and reliable products with higher performance. At the electronic component level, this translates to components with increased I/Os and reduced footprints, and on the package substrate and printed circuit board (PCB) level, to the use of high density interconnects (HDIs). HDI technology makes use of microvias as interconnects between different conductor layers. According to IPC standards, microvias are blind or buried vias that are equal to or less than 150 μm in diameter. Advances in miniaturized electronic devices have led to the evolution of microvias from single-level to stacked structures that intersect multiple HDI layers. A stacked microvia is usually filled with electroplated copper to make electrical interconnections and provide structural support. A challenge for HDI circuit board processing is to fabricate microvias without generating defects in the deposited copper structures. Firstly, the copper plating process can easily generate voids in microvias. When voids are present, localized stress concentrations within the electrodeposited copper structure can degrade the reliability of microvias. Secondly, poor quality of electroless copper (a process step following microvia hole drilling and prior to electrolytic copper plating, that makes the microvia hole conductive) results in inferior bonding between the base of the microvia and the target pad underneath the microvia. Microvia base and target pad interface separation is a common failure observed in HDI circuit boards. The objectives of this dissertation are to determine the effects of voids on the lifetime of copper-filled stacked microvias, and to develop an analytical model that the electronics industry can use to predict microvia fatigue life and assess risks associated with production and use of the latest generation of HDI circuit boards. The dissertation also aims to quantitatively address the factors that affect microvia interface separation. A parametric study was conducted to investigate the effects of voids on the thermo-mechanical reliability of copper-filled stacked microvias using 3-D finite element analysis and strain-based fatigue life estimation. It was found that microvia fatigue life is affected by geometrical void characteristics, such as shape, size, and location; microvia aspect ratio; and material properties of dielectric layers. Large voids decrease the lifetime of microvias—for example, a 16% conical void results in a microvia fatigue life that is only 1.4% of that of a non-voided microvia. Moreover, microvia aspect ratio and z-axis coefficient of thermal expansion (CTE) of the HDI dielectric material are critical parameters for the lifetime. The fatigue life of a voided microvia of 0.25 aspect ratio is more than two orders of magnitude longer than the fatigue life of a voided microvia of 0.75 aspect ratio with the same void size. An increase of the z-axis CTE by 40% (from 50 ppm/°C to 70 ppm/°C) decreases the microvia fatigue life by 95%. As an outgrowth of this study, a microvia virtual qualification method was proposed. Using the combination of finite element analysis and fatigue life estimation, the required amount of HDI board reliability testing will be reduced, cutting overall development time and cost. The factors that affect microvia fatigue life were examined, and a design of experiment (finite element simulation) was performed to quantify the effects of those factors on microvia lifetime in terms of cycles to failure. A second-order regression life prediction model was developed using response surface mothed (RSM) to predict cycles to failure of copper-filled stacked microvias under thermal loading. The life prediction model accounts for not only the microvia design parameters and material properties, but also voiding defects introduced during the manufacturing process. The model can predict cycles-to-failure of microvias without voids and with voids of different sizes. The electronics industry can use this model as a convenient and inexpensive tool for HDI design and process validation. This is the first known regression model for copper-filled stacked microvia life prediction. Finally, the factors that affect microvia interface separation were quantitatively addressed. Finite element modeling was used to simulate microvias with imperfect electroless copper layers. This study revealed how thermal loadings and structure flaws (in terms of initial crack length) affect the chance of microvia interface separation.