A. James Clark School of Engineering

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The collections in this community comprise faculty research works, as well as graduate theses and dissertations.

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    Effect of Encapsulation on Electrolyte Leakage in Aluminum Electrolytic Capacitors Under Constant Thermal and Electrical Loading
    (2014) Parsa, Ehsan; Dasgupta, Abhijit; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    This study focuses on the influence of encapsulation (with silicone elastomer potting compound) on electrolyte leakage in aluminum electrolytic capacitors. Experiments were conducted on potted capacitors at constant elevated temperature and rated DC voltage, and results were compared to those from a control batch of unpotted capacitors. The weight, ESR and capacitance were periodically monitored. Encapsulation was found to decelerate electrolyte loss rate and ESR degradation. There was an increasingly discernible deceleration of capacitance degradation but the magnitude did not reach statistically significant thresholds within the test period. A simplified axisymmetric finite element model was constructed for theoretical understanding of the electrolyte loss process. The experimental measurements were used to guide the selection of the material properties in the model. The model addresses several possible sources of non-uniformities in the mass flux density in the test specimen: (i) radial nonuniformity of mass transport properties of the rubber seal; and (ii) delamination between the potting compound and the capacitor leads. This model was then used: (i) to conduct parametric investigation of the effect of mass transport properties of the potting compound; and (ii) in conjunction with the experimental results to estimate the electrolyte mass loss from the capacitor through the rubber seal.
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    Characterization of Transient Heating in Power Electronic Devices and its Implications for Die Attached Reliability
    (2012) Smith, Kyle Christopher; McCluskey, Patrick; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Military and commercial interest in the use of power electronics for applications requiring extreme operating conditions and/or placement in extreme environments is driving research to identify and develop packaging technologies that can withstand these conditions. Specifically, there is an interest in the development of packaging technology than can function reliably under transient high power loading conditions. This thesis addresses the unique packaging considerations required for this type of application, with a focus on the implications on the durability of the die attach layer. Simulations of the thermal conditions experienced at the die attach layer for different power pulse magnitudes and durations are presented. A test apparatus and experimental test plan for studying the reliability of die attach materials under high power transient loading is discussed. Studies conducted to validate the test apparatus and characterize die attach reliability are described along with recommendations for further investigation of the reliability issues associated with high power, transient loading conditions.
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    PROBABILISTIC PHYSICS OF FAILURE ASSESSMENT OF THERMOMECHANICAL FATIGUE IN HIGH-I/O AREA-ARRAY INTERCONNECTS
    (2009) Roettele, Shaughn Michael; Dasgupta, Abhijit; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Thermal cycling durability of Plastic ball grid array (PBGA) interconnects is known to decrease as I/O count increases. This is due, in part, to mechanistic effects; such as increasing thermal expansion mismatches between component and PWB, due to increasing package sizes. Failure prediction due to these mechanistic effects is a deterministic process and is based on the load level found in the critical joint (joint with the most severe loading). However, due to probabilistic effects, for example manufacturing variabilities, premature failure may result in one of several joints in the neighborhood of the critical one. Failure probability increases as the number of joints in this critical region increases. Thus, observed failure rates are due to a convolution of deterministic and probabilistic effects. In effect, for large BGAs, deterministic predictions may overestimate interconnect durability. This thesis uses thermal cycling experiments and detailed mechanistic modeling to present a methodology for adjusting deterministic predictions of solder joint failure with a suitable probabilistic correction factor.
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    Development of an Advanced Adhesion Test for Polymer Interfaces
    (2007-11-19) Vickey, Nathan Andrew; Han, Bongtae; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The bond strength of polymer interfaces within packaged microelectronic devices significantly influences their reliability. In the interest of predictive modeling and to facilitate materials selection during the design process, it is highly desirable to be able to distinguish between the adhesive performances of multiple polymer interfaces. However, typical adhesion testing is normally plagued by large deviations in its test results which make drawing statistical conclusions from adhesion strength data difficult. To remedy this, an investigation into the primary sources of variance associated with the pull test was performed. Four primary factors were identified, load alignment, loading rate, bond thickness, and the edge condition. The control of each of these four parameters was targeted during the development of an improved adhesion test technique. The results are an adhesion measurement method which has successfully reduced the scatter in test results from a standard deviation of 50% to approximately 10%.
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    On-Chip Thermoelectric Cooling of Semiconductor Hot Spot
    (2007-08-28) Wang, Peng; Bar-Cohen, Avram; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    The Moore's Law progression in semiconductor technology, including shrinking feature size, increasing transistor density, and faster circuit speeds, is leading to increasing total power dissipations and heat fluxes on silicon chip. Moreover, in recent years, increasing performance has resulted in greater non-uniformity of on-chip power dissipation, creating microscale hot spots that can significantly degrade the processor performance and reliability. Application of conventional thermal packaging technology, developed to provide uniform chip cooling, to such chip designs results in lower allowable chip power dissipation or overcooling of large areas of the chip. Consequently, novel thermoelectric cooler (TEC) has been proposed recently for on-chip hot spot cooling because of its unique ability to selectively cool down the localized microscale hot spot. In this dissertation the potential application of thermoelectric coolers to suppress on-chip hotspots is explored using analytical modeling, numerical simulation, and experimental techniques. Single-crystal silicon is proposed as a potential thermoelectric material due to its high Seebeck coefficient and its thermoelectric cooling performance is investigated using device-level analytical modeling. Integrated on silicon chip as an integral, on-chip thermoelectric cooler, silicon microcooler can effectively reduce the hotspot temperature and its effectiveness is investigated using analytical modeling and numerical simulation, and found to be dependent of doping concentration in silicon, electric contact resistance, hotspot size, hotspot heat flux, die thickness and microcooler size. The other novel on-chip hotspot cooling solution developed in this dissertation is to use a mini-contact enhanced TEC, where the mini-contact pad connects the silicon chip and the TEC to concentrate the thermoelectric cooling power onto a spot of top surface of the silicon chip and therefore significantly improve the hotspot cooling performance. Numerical simulation shows hotspot cooling is determined by thermal contact resistance, thermoelectric element thickness, chip thickness, etc. Package-level experiment demonstrates that spot cooling performance of such mini-contact enhanced TEC can be improved by about 100%.