A. James Clark School of Engineering
Permanent URI for this communityhttp://hdl.handle.net/1903/1654
The collections in this community comprise faculty research works, as well as graduate theses and dissertations.
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Item Engineering a Control System for a Logical Qubit-Scale Trapped Ion Quantum Computer(2023) Risinger, Andrew Russ; Monroe, Christopher R; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Quantum computing is a promising field for continuing to develop new computing capabilities, both in its own right and for continued gains as Moore's Law growth ends.Trapped ion quantum computing is a leading technology in the field of quantum computing, as it combines the important characteristics of high fidelity operations, individual addressing, and long coherence times. However, quantum computers are still in their infancy; the first quantum computers to have more than a handful of quantum bits (qubits) are less than a decade old. As research groups push the boundaries of the number of qubits in a system, they are consistently running into engineering obstacles preventing them from achieving their goals. There is effectively a knowledge gap between the physicists who have the capability to push the field of quantum computing forward, and the engineers who can design the large-scale & reliable systems that enable pushing those envelopes. This thesis is an attempt to bridge that gap by framing trapped ion quantum computing in a manner accessible to engineers, as well as improving on the state-of-the-art in quantum computer digital and RF control systems. We also consider some of the practical and theoretical engineering challenges that arise when developing a leading-edge trapped ion quantum computer capable of demonstrating error-corrected logical qubits, using trapped Ytterbium-171 qubits.There are many fundamental quantum operations that quantum information theory assumes, yet which are quite complicated to implement in reality. First, we address the time cost of rearranging a chain of ions after a scrambling collision with background gases. Then we consider a gate waveform generator that reduces programming time while supporting conditional quantum gates. Next, we discuss the development of a digital control system custom-designed for quantum computing and quantum networking applications. Finally, we demonstrate experimental results of the waveform generator executing novel gate schemes on a chain of trapped ions. These building blocks together will unlock new capabilities in the field of trapped ion quantum computers.Item CROSS-LAYER CUSTOMIZATION FOR LOW POWER AND HIGH PERFORMANCE EMBEDDED MULTI-CORE PROCESSORS(2010) Yu, Chenjie; Petrov, Peter; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Due to physical limitations and design difficulties, computer processor architecture has shifted to multi-core and even many-core based approaches in recent years. Such architectures provide potentials for sustainable performance scaling into future peta-scale/exa-scale computing platforms, at affordable power budget, design complexity, and verification efforts. To date, multi-core processor products have been replacing uni-core processors in almost every market segment, including embedded systems, general-purpose desktops and laptops, and super computers. However, many issues still remain with multi-core processor architectures that need to be addressed before their potentials could be fully realized. People in both academia and industry research community are still seeking proper ways to make efficient and effective use of these processors. The issues involve hardware architecture trade-offs, the system software service, the run-time management, and user application design, which demand more research effort into this field. Due to the architectural specialties with multi-core based computers, a Cross-Layer Customization framework is proposed in this work, which combines application specific information and system platform features, along with necessary operating system service support, to achieve exceptional power and performance efficiency for targeted multi-core platforms. Several topics are covered with specific optimization goals, including snoop cache coherence protocol, inter-core communication for producer-consumer applications, synchronization mechanisms, and off-chip memory bandwidth limitations. Analysis of benchmark program execution with conventional mechanisms is made to reveal the overheads in terms of power and performance. Specific customizations are proposed to eliminate such overheads with support from hardware, system software, compiler, and user applications. Experiments show significant improvement on system performance and power efficiency.Item Speculative Data Distribution in Shared Memory Multiprocessors(2008-04-16) Leventhal, Sean; Franklin, Manoj; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)This work explores the possibility of using speculation at the directories in a cache coherent non-uniform memory access multiprocessor architecture to improve performance by forwarding data to their destinations before requests are sent. It improves on previous consumer prediction techniques, showing how to construct a predictor that can handle a tradeoff of accuracy and coverage. This dissertation then explores the correct time to perform consumer prediction, and show how a directory protocol can incorporate such a scheme. The consumer prediction enhanced protocol that is developed is able to reduce the runtime of a set of scientific benchmarks by 10%-20%, without substantially reducing the runtime of other benchmarks; specifically, those benchmarks feature simple phased behavior and regularly distribute data to more than two processors. This work then explores the interaction of consumer prediction with two other forms of prediction, migratory prediction and last touch prediction. It demonstrates a mechanism by which migratory prediction can be implemented using only the storage elements already present in a consumer predictor. By combining this migratory predictor with a consumer predictor, it is possible to produce greater speedups than did either individually. Finally, the signatures of the last touch predictor can be applied to improve the performance of consumer prediction.Item Applying Perceptrons to Speculation in Computer Architecture(2007-04-05) Black, Michael David; Franklin, Manoj; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Speculation plays an ever-increasing role in optimizing the execution of programs in computer architecture. Speculative decision-makers are typically required to have high speed and small size, thus limiting their complexity and capability. Because of these restrictions, predictors often consider only a small subset of the available data in making decisions, and consequently do not realize their potential accuracy. Perceptrons, or simple neural networks, can be highly useful in speculation for their ability to examine larger quantities of available data, and identify which data lead to accurate results. Recent research has demonstrated that perceptrons can operate successfully within the strict size and latency restrictions of speculation in computer architecture. This dissertation first studies how perceptrons can be made to predict accurately when they directly replace the traditional pattern table predictor. Several weight training methods and multiple-bit perceptron topologies are modeled and evaluated in their ability to learn data patterns that pattern tables can learn. The effects of interference between past data on perceptrons are evaluated, and different interference reduction strategies are explored. Perceptrons are then applied to two speculative applications: data value prediction and dataflow critical path prediction. Several new perceptron value predictors are proposed that can consider longer or more varied data histories than existing table-based value predictors. These include a global-based local predictor that uses global correlations between data values to predict past local values, a global-based global predictor that uses global correlations to predict past global values, and a bitwise predictor that can use global correlations to generate new data values. Several new perceptron criticality predictors are proposed that use global correlations between instruction behaviors to accurately determine whether instructions lie on the critical path. These predictors are evaluated against local table-based approaches on a custom cycle-accurate processor simulator, and are shown on average to have both superior accuracy and higher instruction-per-cycle performance. Finally, the perceptron predictors are simulated using the different weight training approaches and multiple-bit topologies. It is shown that for these applications, perceptron topologies and training approaches must be selected that respond well to highly imbalanced and poorly correlated past data patterns.Item Performance Characteristics of an Intelligent Memory System(2004-07-07) Teller, Justin Stevenson; Silio, Charles; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)The memory system is increasingly becoming a performance bottleneck. Several intelligent memory systems, such as the ActivePages, DIVA, and IRAM architectures, have been proposed to alleviate the processor-memory bottleneck. This thesis presents the Memory Arithmetic Unit and Interface (MAUI) architecture. The MAUI architecture combines ideas of the ActivePages, DIVA, and ULMT architectures into a new intelligent memory system. A simulator of the MAUI architecture was added to the SimpleScalar v4.0 toolset. Simulation results indicate that the MAUI architecture provides the largest application speedup when operating on datasets that are much too large to fit in the processor's cache and when integrated with systems using a high performance DRAM system and a low performance processor. By coupling a 2000 MHz processor with an 800 MHz DRDRAM DRAM system, the Stream benchmark, originally written by John D. McCalpin, completed 121% faster in simulations when optimized to use the MAUI architecture.