A. James Clark School of Engineering

Permanent URI for this communityhttp://hdl.handle.net/1903/1654

The collections in this community comprise faculty research works, as well as graduate theses and dissertations.

Browse

Subject: search.filters.subject.Low power

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Power Minimization in QoS Sensitive Systems
    (IEEE, 2004-06) Wong, Jennifer L; Qu, Gang; Potkonjak, Miodrag
    The majority of modern multimedia and mobile systems have two common denominators: quality-of-service (QoS) requirements, such as latency and synchronization, and strict energy constraints. However, until now no synthesis techniques have been proposed for the design and efficient use of such systems.We have two main objectives: conceptual and synthesis. The conceptual objective is to develop a generic practical technique for the automatic development of online adaptive algorithms from efficient off-line algorithms using statistical techniques. The synthesis objective is to introduce the first design technique for QoS low-power synthesis. We introduce a system of provablyoptimal techniques that minimize energy consumption of streamoriented applications under two main QoS metrics: latency and synchronization. Specifically, we study how multiple voltages can be used to simultaneously satisfy hardware constraints and minimize power consumption while preserving the requested level of QoS. The purpose of the off-line algorithm is threefold. First, it is used as input to statistical software which is used to identify important and relevant parameters of the processes. Second, the algorithm provides buffer occupancy rate indicators. Lastly, it provides a way to combine buffer occupancy and QoS metrics to form a fast and efficient online algorithm. The effectiveness of the algorithms is demonstrated on a number of standard multimedia benchmarks.
  • Thumbnail Image
    Item
    Eliminating Inter-proces Cache Interference Through Reconfigurability for Real-time and Low Power Embedded Systems
    (2007-08-09) Reddy, Rakesh; Petrov, Peter; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    This study proposes a technique which leverages data cache reconfigurability to address the problem of cache interference in multitasking embedded systems. Modern embedded systems often implement complex applications, comprising of multiple execution tasks with heavy memory requirements. Data caches are necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache outcomes in multi-tasking environments are difficult to predict, thus resulting in very poor real-time performance guarantees. Additionally, caches contribute to a significant amount of power. We study the effect that multiple concurrent tasks have on the cache and, subsequently, propose a technique which leverages work on reconfigurable cache architectures to eliminate cache interference and reduce power consumption using application specific information. By mapping parallel tasks to different cache partitions, inter-task interference is completely eliminated with minimal performance impact. Furthermore, both leakage and dynamic power is significantly improved.