A. James Clark School of Engineering

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Using Many-Core Computing to Speed Up De Novo Transcriptome Assembly
(2016) O'Brien, Sean; Vishkin, Uzi; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
The central dogma of molecular biology implies that DNA holds the blueprint which determines an organism's structure and functioning. However, this blueprint can be read in different ways to accommodate various needs, depending on a cell's location in the body, its environment, or other external factors. This is accomplished by first transcribing DNA into messenger RNA (mRNA), and then translating mRNA into proteins. The cell regulates how much each gene is transcribed into mRNA, and even which parts of each gene is transcribed. A single gene may be transcribed in different ways by splicing out different parts of the sequence. Thus, one gene may be transcribed into many different mRNA sequences, and eventually into different proteins. The set of mRNA sequences found in a cell is known as its transcriptome, and it differs between tissues and with time. The transcriptome gives a biologist a snapshot of the cell's state, and can help them track the progression of disease, etc. Some modern methods of transcriptome sequencing give only short reads of the mRNA, up to 100 nucleotides. In order to reconstruct the mRNA sequences, one must use an assembly algorithm to stitch these short reads back into full length transcripts. De novo transcriptome assemblers are an important family of transcriptome assemblers. Such assemblers reconstruct the transcriptome without using a reference genome to align to and are, therefore, computationally intensive. We present here a de novo transcriptome assembler designed for a parallel computer architecture, the XMT architecture. With this assembler we produce speedups over existing de novo transcriptome assemblers without sacrificing performance on traditional quality metrics.
Can Cooling Technology Save Many-Core Parallel Programming from Its Programming Woes?
(2015-10-16) O'Brien, Sean; Vishkin, Uzi; Edwards, James; Waks, Edo; Yang, Bao
This paper is advancing the following premise (henceforth, "vision"): that it is feasible to greatly enhance data movement in the short term, and do it in ways that would be both power efficient and pragmatic in the long term. The paper spells this premise out in greater detail: 1. it is feasible to build first generations of a variety of (power-inefficient) designs for which data movement will not be a restriction and begin application software development for them; 2. growing reliance on silicon compatible photonic technologies, and feasible advances in them with proper investment, will allow reduction of power consumption in these design by several orders of magnitude; 3. successful high performance application software, the ease of programming demonstrated and growing adoption by customers, software vendors and programmers will incentivize (hardware vendor) investment in new application-software-compatible generations of these designs (a new "software spiral" a la former Intel CEO, Andy Grove) with further reduction of power consumption in each generation; 4. microfluidic cooling is instrumental for enabling item 1, as well as for midwifing this overall vision. The opening paragraph of the paper provides a preamble to that vision, the body of the paper supports it and the paragraph "Moore's-Law-type vision" summarizes it. The scope of the paper is a bit forward looking and it may not exactly fit any particular community. However, its new directions for interaction among architecture and programming may suggest new horizons for representing and exposing a greater variety of data and task parallelism.
Feasibility Study of Scaling an XMT Many-Core
(2015-01-19) O'Brien, Sean; Vishkin, Uzi; Edwards, James; Waks, Edo; Yang, Bao
The reason for recent focus on communication avoidance is that high rates of data movement become infeasible due to excessive power dissipation. However, shifting the responsibility of minimizing data movement to the parallel algorithm designer comes at significant costs to programmer’s productivity, as well as: (i) reduced speedups and (ii) the risk of repelling application developers from adopting parallelism. The UMD Explicit Multi-Threading (XMT) framework has demonstrated advantages on ease of parallel programming through its support of PRAM-like programming, combined with strong, often unprecedented speedups. Such programming and speedups involve considerable data movement between processors and shared memory. Another reason that XMT is a good test case for a study of data movement is that XMT permits isolation and direct study of most of its data movement (and its power dissipation). Our new results demonstrate that an XMT single-chip many-core processor with tens of thousands of cores and a high throughput network on chip is thermally feasible, though at some cost. This leads to a perhaps game-changing outcome: instead of imposing upfront strict restrictions on data movement, as advocated in a recent report from the National Academies, opt for due diligence that accounts for the full impact on cost. For example, does the increased cost due to communication avoidance (including programmer’s productivity, reduced speedups and desertion risk) indeed offset the cost of the solution we present? More specifically, we investigate in this paper the design of an XMT many-core for 3D VLSI with microfluidic cooling. We used state-of-the-art simulation tools to model the power and thermal properties of such an architecture with 8k to 64k lightweight cores, requiring between 2 and 8 silicon layers. Inter-chip communication using silicon compatible photonics is also considered. We found that, with the use of microfluidic cooling, power dissipation becomes a cost issue rather than a feasibility constraint. Robustness of the results is also discussed.

A. James Clark School of Engineering

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