A. James Clark School of Engineering

Permanent URI for this communityhttp://hdl.handle.net/1903/1654

The collections in this community comprise faculty research works, as well as graduate theses and dissertations.

Browse

Filters

2003 - 20042

Settings

Author: search.filters.author.Iyer, Bharath

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs
    (2004-06) Iyer, Bharath; Srinivasan, Sadagopan; Jacob, Bruce
    VLIW architecture based DSPs have become widespread due to the combined benefits of simple hardware and compiler-extracted instruction-level parallelism. However, the VLIW instruction set architecture and its hardware implementation are tightly coupled, especially so for Non-Unit Assumed Latency (NUAL) VLIWs. The problem of object code compatibility across processors having different numbers of functional units or hardware latencies has been the Achilles' heel of this otherwise powerful architecture. In this paper, we propose eXtended Split-Issue (XSI), a novel mechanism that breaks the instruction packet syntax of an NUAL VLIW compiler without violating the dataflow dependences. XSI provides a designer the freedom of disassociating the hardware implementation of the NUAL VLIW processor from the instruction set architecture. Further, we investigate fairly radical (in the context of VLIW) changes to the hardware—like removing an adder, adding a multiplier, and incorporating simultaneous multithreading (SMT)—to show that our technique works for a variety of hardware configurations without compromising on performance. The technique can be used in both single-threaded and multi-threaded architectures to achieve a level of flexibility heretofore unavailable in the VLIW arena.
  • Thumbnail Image
    Item
    Extended Split-Issue Mechanism in VLIW DSPs to Support SMT and Hardware-ISA Decoupling
    (2003-12-04) Iyer, Bharath; Jacob, Bruce; Electrical Engineering
    The use of VLIW architecture has become widespread in the DSP arena due to the combined benefits of simple hardware and instruction level parallelism extracted by the compiler. In an attempt to extract higher processing throughput we investigate simultaneous multithreading (SMT) to exploit thread-level parallelism in a VLIW DSP. We propose an extended split-issue mechanism that allows us to break the instruction packet syntax of a VLIW compiler without violating the dataflow dependences. The capability to break VLIW instruction packets gives us greater freedom in scheduling instructions from different threads based on functional unit availability. We find that the SMT VLIW DSP provides significant processing throughput gains, which could also be traded-off for rich energy savings. The extended split-issue mechanism also provides us with an unprecedented, albeit limited, degree of freedom in disassociating the hardware implementation of the VLIW processor with the instruction set architecture (ISA). Simulation results show that the ability to modify the hardware implementation based on the utilisation statistics presents a new dimension that can be exploited to improve the efficiency of the processor.