Institute for Systems Research
Permanent URI for this communityhttp://hdl.handle.net/1903/4375
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Item Enhancing LZW Coding Using a Variable-Length Binary Encoding(1995) Acharya, Tinku; JaJa, Joseph F.; ISRWe present here a methodology to enhance the LZW coding for text compression using a variable-length binary encoding scheme. The basic principle of this encoding is based on allocating a set of prefix codes to a set of integers growing dynamically. The prefix property enables unique decoding of a string of elements from this set. We presented the experimental results to show the effectiveness of this variable-length binary encoding scheme.Item VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression(1992) Yu, S-S.; Kolagotla, Ravi K.; JaJa, Joseph F.; ISRWe describe a pipelined systolic architecture for implementing predictive Tree-Searched Vector Quantization (PTSVQ) for real- time image and speech coding applications. This architecture uses identical processors for both the encoding and decoding processes. the overall design is regular and the control is simple. Input data is processed at a rate of 1 pixel per clock cycle, which allows real-time processing of images at video rates. We implemented these processors using 1.2um CMOS technology. Spice simulations indicate correct operation at 40 MHz. Prototype version of these chips fabricated using 2um CMOS technology work at 20 MHz.Item Systolic Architectures for Finite-State Vector Quantization(1991) Kolagotla, Ravi K.; Yu, S-S.; JaJa, Joseph F.; ISRWe present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line- scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024 x 1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these FSTSVQ processors.Item VLSI Implementation of a Tree Searched Vector Quantizer(1990) Kolagotla, Ravi K.; Yu, S.S.; JaJa, Joseph F.; ISRThe VLSI design and implementation of a Tree Searched Vector Quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using MOSIS' 2mm N- well process on a 7.9mm x 9.2mm die. Each processor chip contains 25,000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 10 MHz. These processors will be used in an adaptive image compression system to compress LANDSAT images.