Institute for Systems Research Technical Reports
Permanent URI for this collectionhttp://hdl.handle.net/1903/4376
This archive contains a collection of reports generated by the faculty and students of the Institute for Systems Research (ISR), a permanent, interdisciplinary research unit in the A. James Clark School of Engineering at the University of Maryland. ISR-based projects are conducted through partnerships with industry and government, bringing together faculty and students from multiple academic departments and colleges across the university.
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Item Fluidic Cooling and Gate Size Co-optimization in 3D-ICs: Pushing the Power-Performance Limits(2013) Shi, Bing; Srivastava, Ankur; Srivastava, AnkurThe performance improvement of modern computer systems is usually accompanied by increased computational power and thermal hotspots, which in turn limit the further improvement of system performance. In 3D-ICs, this thermal problem is significantly exacerbated, necessitating the need for active cooling approaches such as micro-fluidic cooling. This paper investigates a co-optimization approach for 3D-IC electric (gate sizing) and cooling design that fully exploits the interdependency between power, temperature and circuit delay to push the powerperformance tradeoff beyond conventional limits. We propose a unified formulation to model this co-optimization problem and use an iterative optimization approach to solve the problem. The experimental results show a fundamental power-performance improvement, with 12% power saving and 16% circuit speedup.Item TSV-Constrained Micro-Channel Infrastructure Design for Cooling Stacked 3D-ICs(2011-05-11) Shi, Bing; Srivastava, AnkurMicro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence of TSVs which form obstacles to the micro-channels prevents distribution of straight micro-channels. In this paper, we investigate the methodology of designing TSV-constrained micro-channel infrastructure. Specifically, we decide the locations and geometry of micro-channels with bended structure so that it's cooling e®ectiveness is maximized. Our micro-channel structure could achieve up to 87% pumping power saving compared with the micro-channel structure using straight channels.Item Dynamic Thermal Management Considering Accurate Temperature-Leakage Interdependency(2010-07) Shi, Bing; Srivastava, Ankur; Ankur, SrivastavaIn this paper, we develop an accurate dynamic thermal management DTM approach considering the interdependency of temperature and leakage. By modeling the leakage-thermal interdependence as a quadratic polynomial, we develop accurate analytical equations that capture the thermal transient. We also identify all the situations in which thermal runaway would occur, which should be avoided by DTM.We then present a discrete dynamic programming algorithm that performs thermal-aware task and speed scheduling using the model we derived.Compared to a linear leakage-thermal model, owing to our more accurate model, our scheme resulted in 18.2% better performance while maintaining the temperature below constraint.Item Unified Datacenter Power Management Considering On-Chip and Air Temperature Constraints(2010) Shi, Bing; Srivastava, Ankur; Srivastava, AnkurThe current approaches for datacenter power management (workload scheduling, CPU speed control, etc) focus primarily on maintaining the air temperature surrounding servers to be within the manufacturer specified constraint. This is problematic since several CPUs may still be violating the on-chip thermal constraint thereby leading to reliability loss. The primary objective of this work is to develop a unified approach for datacenter power optimization (by controlling the CPU speeds) which accounts for both the silicon level temperature of the VLSI components such as CPUs and the air temperature that directly impacts the reliability of other devices such as disks, and also the performance delivered. Our algorithm follows a two step approach: optimally solving a convex approximation that assigns continuous frequency values to all CPUs and a discretization step for legalization of the assigned frequencies. The experimental results indicate that our method guarantees both on-chip CPU and off-chip air temperature to be within temperature constraints. However, the traditional approach of constraining only air temperature will result in on-chip CPU temperature violation on about 40% of the CPUs, or 42% more power consumption to pull the CPU temperature back within constraint by increasing the HVAC cooling.