Institute for Systems Research Technical Reports

Permanent URI for this collectionhttp://hdl.handle.net/1903/4376

This archive contains a collection of reports generated by the faculty and students of the Institute for Systems Research (ISR), a permanent, interdisciplinary research unit in the A. James Clark School of Engineering at the University of Maryland. ISR-based projects are conducted through partnerships with industry and government, bringing together faculty and students from multiple academic departments and colleges across the university.

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Author: search.filters.author.Kolagotla, Ravi K.Subject: search.filters.subject.data compression

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    Design and Implementation of Systolic Architectures for Vector Quantization
    (1992) Kolagotla, Ravi K.; JaJa, J.; ISR
    Vector Quantization has emerged as an efficient data compression tool for compressing speech and image data. We develop efficient systolic architecture implementations of Tree-Search Vector Quantizers (TSVQ) and Finite-State Vector Quantizers (FSVQ). Our TSVQ architecture consists of a linear array of processors, each processor performing the computations required at one level of the binary tree. Encoding is performed in a pipeline fashion with each processor generating a portion of the path through the tree. The final processor returns the complete index. Data and control flow from processor to processor along the pipeline and no global control signals are needed. The FSVQ architecture for image coding consists of a linear array of TSVQ processors with each processor operating on a separate column of the input image. The number of processors needed depends on the latency of the TSVQ and is independent of the size of the image. We also develop implementations of Scalar and Inverse Scalar Quantizers for use in transform coding applications.
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    VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression
    (1992) Yu, S-S.; Kolagotla, Ravi K.; JaJa, Joseph F.; ISR
    We describe a pipelined systolic architecture for implementing predictive Tree-Searched Vector Quantization (PTSVQ) for real- time image and speech coding applications. This architecture uses identical processors for both the encoding and decoding processes. the overall design is regular and the control is simple. Input data is processed at a rate of 1 pixel per clock cycle, which allows real-time processing of images at video rates. We implemented these processors using 1.2um CMOS technology. Spice simulations indicate correct operation at 40 MHz. Prototype version of these chips fabricated using 2um CMOS technology work at 20 MHz.
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    Systolic Architectures for Finite-State Vector Quantization
    (1991) Kolagotla, Ravi K.; Yu, S-S.; JaJa, Joseph F.; ISR
    We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line- scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024 x 1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these FSTSVQ processors.
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    VLSI Implementation of a Tree Searched Vector Quantizer
    (1990) Kolagotla, Ravi K.; Yu, S.S.; JaJa, Joseph F.; ISR
    The VLSI design and implementation of a Tree Searched Vector Quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using MOSIS' 2mm N- well process on a 7.9mm x 9.2mm die. Each processor chip contains 25,000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 10 MHz. These processors will be used in an adaptive image compression system to compress LANDSAT images.