Computer Science Theses and Dissertations
Permanent URI for this collectionhttp://hdl.handle.net/1903/2756
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Item MODEL-BASED SYSTEMS ENGINEERING SIMULATION FRAMEWORK FOR ROBOT GRASPING(2021) Menaka Sekar, Praveen Kumar; Baras, John S; Systems Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Constant rise in industrial usage of robots for commercial applications has led to the need for rapid, efficient, and reliable robotic system development processes. Integration of tools from various disciplines to perform design space exploration,taking into consideration the stakeholder and system requirements, is one major step in regards to this. In this thesis, we apply Model-Based Systems Engineering (MBSE) principles to a simple pick and place task. We do this by integrating Cameo Systems Modeling Language (SysML) tool, CoppeliaSim robot simulator, and Gurobi Optimizer to facilitate and accelerate the design process for a robot grasping system. A simulation based Verification & Validation approach supports design space exploration to obtain optimal design solutions, thereby leading to successful and profitable deployment and operation.Item Identifying and Comparing Subproblems in Factory Design Processes(2018) Kanagat, Pranay; Herrmann, Jeffrey W; Systems Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)When a design team faces a problem of designing a complex system, they are required to make several decisions. Because such design problems are difficult to solve all at once, teams often decompose the design problem into several smaller subproblems. This thesis discusses the results of a study designed to understand how design teams decompose a factory redesign problem into sets of related subproblems and compare the subproblems obtained for each design team. This exploratory study analyzed the design activities of six teams of professionals and used clustering to group the variables that the design teams considered. It was found that the design teams used different decomposition strategies and different subproblems, but they more often considered subproblems with design variables of the same type, and some teams followed a top-down design process.Item FURTHERING PSYCHOLOGICALUNDERSTANDING AND OVERCOMINGCOST-RELATED SHOPPING CARTABANDONMENT WITH GEOLOCATIONCROWDSOURCING(2018) Chang, Chiun-yao; Golbeck, Jennifer; Computer Science; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Online shopping cart abandonment continues to be a widely studied phenomenon in the e-commerce space. While many existing studies are designed to analyze a breadth of factors, our specialized study aims to further our understanding of purchase hesitation and subsequent cart abandonment specifically caused by shipping fees. In order to explore shipping fee-related purchase hesitation, we employed a two part study in which we 1) collected data regarding the amount of additional fees a user is willing to pay at different price points as well as the user's psychological responses to these fees, then we 2) integrated crowdsourcing techniques into the results of part 1 and proposed a new interaction model, CrowdShop, that aims to crowdsource users' orders together based on geo-location proximity in order to reach a minimum free shipping threshold. Furthermore, we presented CrowdShop as a functioning prototype to gauge user response and sentiment. In both parts of the study, we employed a grounded-theory approach along with statistical methods for the analysis of the data. In order to reach a free shipping threshold for online orders, we found that many users combine purchasing efforts with closely-located family members and friends. However, user success of reaching a minimum order amount was hindered by the manual nature of such a collaboration. Through user testing sessions, we received positive responses in favor of Crowdshop's ability to streamline and automate collaboration efforts. However, there still exists opportunities for further development regarding user concerns with CrowdShop.Item Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions(2015) Awan, Sana Mehmood; Qu, Gang; Systems Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.