Enhancing Power Efficient Design Techniques in Deep Submicron Era
| dc.contributor.advisor | Qu, Gang | en_US |
| dc.contributor.author | Gu, Junjun | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2011-10-08T05:32:42Z | |
| dc.date.available | 2011-10-08T05:32:42Z | |
| dc.date.issued | 2011 | en_US |
| dc.description.abstract | Excessive power dissipation has been one of the major bottlenecks for design and manufacture in the past couple of decades. Power efficient design has become more and more challenging when technology scales down to the deep submicron era that features the dominance of leakage, the manufacture variation, the on-chip temperature variation and higher reliability requirements, among others. Most of the computer aided design (CAD) tools and algorithms currently used in industry were developed in the pre deep submicron era and did not consider the new features explicitly and adequately. Recent research advances in deep submicron design, such as the mechanisms of leakage, the source and characterization of manufacture variation, the cause and models of on-chip temperature variation, provide us the opportunity to incorporate these important issues in power efficient design. We explore this opportunity in this dissertation by demonstrating that significant power reduction can be achieved with only minor modification to the existing CAD tools and algorithms. First, we consider peak current, which has become critical for circuit's reliability in deep submicron design. Traditional low power design techniques focus on the reduction of average power. We propose to reduce peak current while keeping the overhead on average power as small as possible. Second, dual Vt technique and gate sizing have been used simultaneously for leakage savings. However, this approach becomes less effective in deep submicron design. We propose to use the newly developed process-induced mechanical stress to enhance its performance. Finally, in deep submicron design, the impact of on-chip temperature variation on leakage and performance becomes more and more significant. We propose a temperature-aware dual Vt approach to alleviate hot spots and achieve further leakage reduction. We also consider this leakage-temperature dependency in the dynamic voltage scaling approach and discover that a commonly accepted result is incorrect for the current technology. We conduct extensive experiments with popular design benchmarks, using the latest industry CAD tools and design libraries. The results show that our proposed enhancements are promising in power saving and are practical to solve the low power design challenges in deep submicron era. | en_US |
| dc.identifier.uri | http://hdl.handle.net/1903/11869 | |
| dc.subject.pqcontrolled | Computer engineering | en_US |
| dc.subject.pquncontrolled | deep submicron technology | en_US |
| dc.subject.pquncontrolled | logic synthesis | en_US |
| dc.subject.pquncontrolled | low power design | en_US |
| dc.subject.pquncontrolled | mechanical stress | en_US |
| dc.subject.pquncontrolled | peak current | en_US |
| dc.subject.pquncontrolled | temperature-aware design | en_US |
| dc.title | Enhancing Power Efficient Design Techniques in Deep Submicron Era | en_US |
| dc.type | Dissertation | en_US |
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