system synthesis for image processing applications
| dc.contributor.advisor | Bhattacharyya, Shuvra S. | en_US |
| dc.contributor.author | Ko, Dong-Ik | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2006-06-14T05:45:25Z | |
| dc.date.available | 2006-06-14T05:45:25Z | |
| dc.date.issued | 2006-04-25 | en_US |
| dc.description.abstract | Over the past few decades, embedded systems have been widely infiltrated into our daily lives. Prominent examples are cellular phones, personal digital assistants, digital television set-top boxes, and web-pads. New kinds of embedded devices are being introduced continually for various purposes. Embedded systems have different combinations and prioritizations of objectives and constraints for their proper design. With the increasing complexity in application functionality, implementation constraints, and optimization objectives, more effective techniques for modeling embedded applications, and for systematically synthesizing implementations become more and more desirable on one hand, and more and more challenging on the other. In this thesis, we focus on the efficient design, implementation, and synthesis of signal processing applications, which form a broad and important class of embedded systems. We place special emphasis in the thesis on the signal processing domain on image processing, a sector that has seen rapidly increasing demand in recent years, but for which present techniques for signal processing design are often lacking in modeling and optimization capability. We propose novel models and algorithms for streamlining scheduling, memory management, and interprocessor communication in embedded multiprocessor implementations of signal processing applications, with the aforementioned emphasis on the image processing domain. For application modeling, we propose two novel modeling techniques called blocked dataflow (BLDF) and dynamic graph topology (DGT). These modeling approaches capture within their respective formal frameworks the structure of block-based image processing operations and reconfigurable, multi-mode dataflow behaviors, respectively. For scheduling, we develop a novel intermediate representation called the pipeline decomposition tree (PDT). The PDT provides efficient representation and analysis of alternative multiprocessing configurations for signal processing applications. We also develop an algorithm, called pipeline decomposition tree scheduling (PDT scheduling), which applies the PDT to systematically derive optimized multiprocessor schedules that employ coarse-grained (task-level) pipelining, which is an especially useful form of parallelism for signal processing. To optimize interprocessor communication, we develop two novel post-optimization techniques for hardware resource mapping and software synthesis. The suite of techniques presented in this thesis address image processing system optimization at key phases in the design process and lead to significant improvements in performance and cost. | en_US |
| dc.format.extent | 3360840 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/3445 | |
| dc.language.iso | en_US | |
| dc.subject.pqcontrolled | Engineering, Electronics and Electrical | en_US |
| dc.subject.pqcontrolled | Computer Science | en_US |
| dc.subject.pquncontrolled | Dataflow based modeling | en_US |
| dc.subject.pquncontrolled | Embedded system optimization | en_US |
| dc.subject.pquncontrolled | Constraints aware multiprocessor scheduling | en_US |
| dc.subject.pquncontrolled | DSP system modeling and synthesis | en_US |
| dc.subject.pquncontrolled | Hardware and software Co-design | en_US |
| dc.subject.pquncontrolled | Pipeline based scheduling | en_US |
| dc.title | system synthesis for image processing applications | en_US |
| dc.type | Dissertation | en_US |
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