Identifying Reordering Transformations That Minimize Idle Processor Time

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dc.contributor.authorKelly, Wayneen_US
dc.contributor.authorPugh, Williamen_US
dc.date.accessioned2004-05-31T21:03:07Z
dc.date.available2004-05-31T21:03:07Z
dc.date.created1995-02en_US
dc.date.issued1998-10-15en_US
dc.format.extent223562 bytes
dc.format.mimetypeapplication/postscript
dc.identifier.urihttp://hdl.handle.net/1903/426
dc.language.isoen_US
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_US
dc.relation.isAvailableAtUniversity of Maryland (College Park, Md.)en_US
dc.relation.isAvailableAtTech Reports in Computer Science and Engineeringen_US
dc.relation.isAvailableAtComputer Science Department Technical Reportsen_US
dc.relation.ispartofseriesUM Computer Science Department; CS-TR-3431en_US
dc.titleIdentifying Reordering Transformations That Minimize Idle Processor Timeen_US
dc.typeTechnical Reporten_US

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Technical Reports of the Computer Science Department