Performance of On-Line Learning Methods in Predicting Multiprocessor
Memory Access Patterns
Performance of On-Line Learning Methods in Predicting Multiprocessor
Memory Access Patterns
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Date
1998-10-15
Authors
Sakr, Majd F.
Levitan, Steven P.
Chiarulli, Donald M.
Horne, Bill G.
Giles, C. Lee
Advisor
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Abstract
Shared memory multiprocessors require reconfigurable interconnection
networks (INs) for scalability. These INs are reconfigured by an IN
control unit. However, these INs are often plagued by undesirable
reconfiguration time that is primarily due to control latency, the
amount of time delay that the control unit takes to decide on a
desired new IN configuration. To reduce control latency, a trainable
prediction unit (PU) was devised and added to the IN controller. The
PU's job is to anticipate and reduce control configuration time, the
major component of the control latency. Three different on-line
prediction techniques were tested to learn and predict repetitive
memory access patterns for three typical parallel processing applications,
the 2-D relaxation algorithm, matrix multiply and Fast Fourier Transform.
The predictions were then used by a routing control algorithm to reduce
control latency by configuring the IN to provide needed memory access
paths before they were requested. Three prediction techniques were used
and tested: 1). a Markov predictor, 2). a linear predictor and 3). a
time delay neural network (TDNN) predictor. As expected, different
predictors performed best on different applications, however, the TDNN
produced the best overall results.
(Also cross-referenced as UMIACS-TR-96-59)