Studying Directory Access Patterns via Reuse Distance Analysis and Evaluating Their Impact on Multi-Level Directory Caches
Studying Directory Access Patterns via Reuse Distance Analysis and Evaluating Their Impact on Multi-Level Directory Caches
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Date
2014-01-13
Authors
Zhao, Minshu
Yeung, Donald
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Abstract
The trend for multicore CPUs is towards increasing core count. One of
the key limiters to scaling will be the on-chip directory cache. Our
work investigates moving portions of the directory away from the cores,
perhaps to off-chip DRAM, where ample capacity exists. While such
multi-level directory caches exhibit increased latency, several aspects
of directory accesses will shield CPU performance from the slower
directory, including low access frequency and latency hiding underneath
data accesses to main memory.
While multi-level directory caches have been studied previously, no work
has of yet comprehensively quantified the directory access patterns
themselves, making it difficult to understand multi-level behavior in
depth. This paper presents a framework based on multicore reuse
distance for studying directory cache access patterns. Using our
analysis framework, we show between 69-93% of directory entries are
looked up only once or twice during their liftimes in the directory
cache, and between 51-71% of dynamic directory accesses are latency
tolerant. Using cache simulations, we show a very small L1 directory
cache can service 80% of latency critical directory lookups. Although a
significant number of directory lookups and eviction notifications must
access the slower L2 directory cache, virtually all of these are latency
tolerant.