Theses and Dissertations from UMD
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New submissions to the thesis/dissertation collections are added automatically as they are received from the Graduate School. Currently, the Graduate School deposits all theses and dissertations from a given semester after the official graduation date. This means that there may be up to a 4 month delay in the appearance of a give thesis/dissertation in DRUM
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Item EFFECTS OF GLASS/EPOXY INTERPHASES ON ELECTRO-CHEMICAL FAILURES IN PRINTED CIRCUIT BOARDS(2018) Sood, Bhanu Pratap; Pecht, Michael G; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Reduction in printed circuit board line spacing and via diameters and the increased density of vias with higher aspect ratios (ratio between the thickness of the board and the size of the drilled hole before plating) are making electronic products increasingly more susceptible to material and manufacturing defects. One failure mechanism of particular concern is conductive anodic filament formation, which typically occurs in two steps: degradation of the resin/glass fiber bond followed by an electrochemical reaction. The glass-resin bond degradation provides a path along which electrodeposition occurs due to electrochemical reactions. Once a path is formed, an aqueous layer, which enables the electrochemical reactions to take place, can develop through the adsorption, absorption, and capillary action of moisture at the resin/fiber interphase. This study describes the experimental and analytical work undertaken to understand the glass-resin delamination and the methods used for analyzing this critical interphase. This study shows that a smaller conductor spacing in reduces the time to failure due to conductive anodic filament formation and that the plated-through-hole to plated-through-hole conductor geometry is more susceptible to conductive anodic filament-induced failures than plated through hole to plane geometries. The results also show that laminates with similar materials and geometries with a 45-degree angle of weave demonstrate a higher resistance to conductive anodic filament formation compared with a 90-degree angle of weave. The study is the first of its kind conducted on FR-4 printed circuit board materials where the pathway formation due to breakage of the organosilane bonds at the glass/resin interphase was evaluated. Using techniques such as force spectroscopy, micro-Fourier transform infrared spectroscopy, scanning quantum interface device microscopy and focused ion beam, evidence of bond breakage and a pathway formation was revealed, poor glass treatment, hydrolysis of the silane glass finish (adsorption of water at the glass fiber/epoxy resin interphase) or repeated thermal cycling contribute to the bond breakage. The technique of applying in-situ resistance measurements during cross-sectioning analysis of printed circuit boards suspected of conductive anodic filament is the first time this method is described in the open literature. This solution addresses the potential problem in destructive physical analysis of grinding away the evidence of the CAF filament and ultimately loosing evidence at the failure site. By applying a subset of the evaluation criteria described in this research, an upfront evaluation of printed circuit board materials can be performed for susceptibility to electro-chemical migration and other failure causes in PCBs that are attributable to the glass/resin interfacial adhesion. Manufacturers can identify board suppliers based on answers to and validation of a series of questions. These questions focus on the necessary requirements of reliable board material manufacturing and are independent of the specifications of the product.Item Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards(2007-05-07) Zhan, Sheng; Pecht, Michael; Mechanical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.