Theses and Dissertations from UMD

Permanent URI for this communityhttp://hdl.handle.net/1903/2

New submissions to the thesis/dissertation collections are added automatically as they are received from the Graduate School. Currently, the Graduate School deposits all theses and dissertations from a given semester after the official graduation date. This means that there may be up to a 4 month delay in the appearance of a give thesis/dissertation in DRUM

More information is available at Theses and Dissertations at University of Maryland Libraries.

Browse

Filters

20181

Settings

Author: search.filters.author.Nallapa Yoge, Dhiraj ReddySubject: search.filters.subject.DRAM

Search Results

Now showing 1 - 1 of 1
  • Thumbnail Image
    Item
    Performance study of various modern DRAM Architectures
    (2018) Nallapa Yoge, Dhiraj Reddy; Jacob, Bruce; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    Several DRAM architectures exist with each differing in their performance, power and cost metrics. This thesis compares the performance and power characteristics of some of such DRAM architectures which are compliant to JEDEC standard DDR protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5 and HBM. To accurately model the differences in performance and power characteristics of these architectures, a new cycle level DRAM memory simulator has been designed and implemented from scratch. Several distinguishing features of these protocols such as - bankgroups in DDR4 and beyond, 32 activation window constraint in GDDR5, granularity of refresh at per rank level vs at per bank level and dual command issue mode in HBM - are modeled and studied for their impact on workload performance and power consumption. The internal structure of DRAM exhibits different kinds of parallelisms such as channel level parallelism, rank level parallelism and bank level parallelism. The type and the degree of parallelism together with the associated DRAM command timing constraints determine the latency and bandwidth characteristics of any DRAM architecture. Abstract studies are performed to determine the potential of each of these parallelisms in attaining the maximum supported pin bandwidth for a set of SPEC 2006 CPU workloads. Finally, several real DRAM architecture designs belonging to each of the above mentioned protocols are studied to quantify their relative performance and power trade-off.