3D Integration, Temperature Effects, and Modeling
| dc.contributor.advisor | Goldsman, Neil | en_US |
| dc.contributor.author | Parker, Latise | en_US |
| dc.contributor.department | Electrical Engineering | en_US |
| dc.contributor.publisher | Digital Repository at the University of Maryland | en_US |
| dc.contributor.publisher | University of Maryland (College Park, Md.) | en_US |
| dc.date.accessioned | 2005-08-03T14:41:19Z | |
| dc.date.available | 2005-08-03T14:41:19Z | |
| dc.date.issued | 2005-05-02 | en_US |
| dc.description.abstract | Practical limits to device scaling are threatening the growth of integrated circuit (IC) technology. A breakthrough architecture is needed in order to realize the increased device density and circuit functionality that future high performance ICs demand. 3D integration is being considered as this breakthrough architecture. In this thesis, the limits to scaling are noted and the feasibility of overcoming these limits using 3D integration is presented. The challenges and considerations, most notably dangerously high chip temperatures, are provided. To address the temperature concern, a mixed-mode simulator that calculates temperature as a function of position on chip is detailed. The simulator captures the important link between individual device and full chip heating. Lastly, circuit simulations and lab experiments are performed to experimentally validate the claims that differences in device activity on chip leads to dangerously high local and overall chip temperatures. | en_US |
| dc.format.extent | 1237055 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/2533 | |
| dc.language.iso | en_US | |
| dc.subject.pqcontrolled | Engineering, Electronics and Electrical | en_US |
| dc.subject.pquncontrolled | 3D Integration | en_US |
| dc.subject.pquncontrolled | chip temperature; | en_US |
| dc.title | 3D Integration, Temperature Effects, and Modeling | en_US |
| dc.type | Thesis | en_US |
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