The Impact of CD Control on Circuit Yield in Sub-Micron Lithography
| dc.contributor.author | Milor, Linda | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:51:41Z | |
| dc.date.available | 2007-05-23T09:51:41Z | |
| dc.date.issued | 1992 | en_US |
| dc.description.abstract | As tolerance as a percent of feature size increases for sub- micron technologies with increased scaling, yield loses due to circuit performance fluctuations will increase. Therefore for sub-micron technologies a tradeoff has to be made between circuit performance yield and the purchase of more expensive processing equipment that can more tightly control critical dimensions. At the same time, the development time of a circuit that is to be manufactured on a process with higher parameter tolerances will increase, and this has to be traded off with the process development time needed to reduce tolerances. In this paper, the performance yield problem for sub-micron technologies is addressed, as it relates to tolerance in geometric feature sizes and alignment. Using a statistical model of process fluctuations, examples are presented showing that different tolerance requirements are needed for different circuits. | en_US |
| dc.format.extent | 547493 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/5283 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; TR 1992-102 | en_US |
| dc.subject | computer aided design | en_US |
| dc.subject | computer aided manufacturing | en_US |
| dc.subject | manufacturability | en_US |
| dc.subject | Systems Integration | en_US |
| dc.title | The Impact of CD Control on Circuit Yield in Sub-Micron Lithography | en_US |
| dc.type | Technical Report | en_US |
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