An Integrated Program Representation for Loop Optimizations

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dc.contributor.advisorBarua, Rajeeven_US
dc.contributor.authorYellareddy, Greeshmaen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2011-07-06T05:49:57Z
dc.date.available2011-07-06T05:49:57Z
dc.date.issued2011en_US
dc.description.abstractInspite of all the advances, automatic parallelization has not entered the general purpose compiling environment for several reasons. There have been two distinct schools of thought in parallelization domain namely, affine and non-affine which have remained incompatible with each other over the years. Thus, a good practical compiler will have to be able to analyze and parallelize any type of code - affine or non-affine or a mix of both. To be able to achieve the best performance, compilers will have to derive the order of transformations best suitable for a given program on a given system. This problem, known as "Phase Ordering", is a very crucial impedance for practical compilers, more so for parallelizing compilers. The ideal compiler should be able to consider various orders of transformations and reason about the performance benefits of the same. In order to achieve such a compiler, in this paper, we propose a unified program representation which has the following characteristics: a) Modular in nature. b) Ability to represent both ane and non-ane transformations. c) Ability to use detailed static run-time estimators directly on the representation.en_US
dc.identifier.urihttp://hdl.handle.net/1903/11510
dc.subject.pqcontrolledComputer Engineeringen_US
dc.subject.pquncontrolledaffineen_US
dc.subject.pquncontrolledautomatic parallelizationen_US
dc.subject.pquncontrolledPDGen_US
dc.subject.pquncontrolledprogram representationen_US
dc.titleAn Integrated Program Representation for Loop Optimizationsen_US
dc.typeThesisen_US

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