Fluidic Cooling and Gate Size Co-optimization in 3D-ICs: Pushing the Power-Performance Limits
| dc.contributor.advisor | Srivastava, Ankur | |
| dc.contributor.author | Shi, Bing | |
| dc.contributor.author | Srivastava, Ankur | |
| dc.date.accessioned | 2013-03-12T13:42:05Z | |
| dc.date.available | 2013-03-12T13:42:05Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | The performance improvement of modern computer systems is usually accompanied by increased computational power and thermal hotspots, which in turn limit the further improvement of system performance. In 3D-ICs, this thermal problem is significantly exacerbated, necessitating the need for active cooling approaches such as micro-fluidic cooling. This paper investigates a co-optimization approach for 3D-IC electric (gate sizing) and cooling design that fully exploits the interdependency between power, temperature and circuit delay to push the powerperformance tradeoff beyond conventional limits. We propose a unified formulation to model this co-optimization problem and use an iterative optimization approach to solve the problem. The experimental results show a fundamental power-performance improvement, with 12% power saving and 16% circuit speedup. | en_US |
| dc.identifier.uri | http://hdl.handle.net/1903/13703 | |
| dc.language.iso | en_US | en_US |
| dc.relation.isAvailableAt | Institute for Systems Research | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.relation.ispartofseries | TR_2013-07 | |
| dc.subject | 3D-IC | en_US |
| dc.subject | micro-fluidic cooling | en_US |
| dc.subject | gate sizing | en_US |
| dc.title | Fluidic Cooling and Gate Size Co-optimization in 3D-ICs: Pushing the Power-Performance Limits | en_US |
| dc.type | Technical Report | en_US |