VLSI Design of Discrete Fourier Transform Processors

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dc.contributor.advisorJaJa, Joseph F.en_US
dc.contributor.authorGoodrich, Todd A.en_US
dc.contributor.departmentISRen_US
dc.date.accessioned2007-05-23T09:49:36Z
dc.date.available2007-05-23T09:49:36Z
dc.date.issued1991en_US
dc.description.abstractA bit-serial cell library is presented which can been used to rapidly implement discrete Fourier transform algorithms in VLSI circuit technology. The design methodology employs systolic summation arrays and multiplier arrays which are bit-serial and fully pipelined. To demonstrate the utility and performance of this cell library, an 8-point discrete Fourier transform (DFT) processor has been designed and implemented as a VLSI chip which at 50 MHz and has a throughput of 2.9 million complex 8-point 16- bit DFT's per second.en_US
dc.format.extent3444840 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/5174
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; MS 1991-3en_US
dc.subjectdistributed information processingen_US
dc.subjectfilteringen_US
dc.subjectimage processingen_US
dc.subjectsignal processingen_US
dc.subjectspeech processingen_US
dc.subjectalgorithmsen_US
dc.subjectcomputational geometryen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectcomputer aided designen_US
dc.subjectautomationen_US
dc.subjectSystems Integrationen_US
dc.titleVLSI Design of Discrete Fourier Transform Processorsen_US
dc.typeThesisen_US

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