Electronic devices are under concurrent loading of the power cycling of the devices and the temperature cycling from the surrounding environment. Temperature histories resultant from these concurrent loading would be a complex temperature cycling with varying cyclic temperature mean and amplitude, as well as spatial thermal gradient.

This study developed modeling approaches and quantified accuracies for predicting solder interconnect life under complex temperature cycling. Three modeling approaches were presented in this study: 1) modeling the strain energy under the resultant complex temperature cycling and employing the energy based fatigue life models; 2) segmenting the resultant complex temperature cycle into multiple simple temperature cycles with a single temperature range for each first, then assessing the life expectancy of the solder interconnect under the segmented simple temperature cycles and at last applying Miner's rule to superpose the damage; 3) estimating solder damage under the resultant complex temperature cycling by a standard temperature cycling with a single temperature range.

Two case studies were included in this thesis: 1) chamber controlled complex temperature cycling with mini cycles occurring at the upper excursion on ceramic leadless chip carriers assembled by Sn36Pb62Ag2 and SnAg3.0Cu0.5 solder (without spatial thermal gradient); 2) combined temperature and power cycling on plastic ball grid array assembled by Sn63Pb37 and SnAg3.0Cu0.5 solder (with spatial thermal gradient). Physical tests were also conducted to quantify the developed modeling approaches.