Browsing by Author "Rim, Chong S."
Now showing 1 - 2 of 2
Results Per Page
Sort Options
Item Graph Bipartization and Via Minimization.(1987) Choi, Hyeong-Ah; Nakajima, Kazuo; Rim, Chong S.; ISRThe vertex- (resp., edge-) deletion graph bipartization problem is the problem of deleting a set of vertices (resp., edges) from a graph so as to make the remaining graph bipartite. In this paper, we first show that the vertex-deletion graph bipartization problem has a solution of size k or less if and only if the edge- deletion graph bipartization problem has a solution of size k or less, when the maximum vertex degree is limited to three. This immediately implies that (1) the vertex-deletion graph bipartization problem is NP-complete for cubic graphs, and (2) the minimum vertex-deletion graph bipartization problem is solvable in polynomial time for planar graphs when the maximum vertex degree is limited to three. We then prove that the vertex- deletion graph bipartization problem is NP-complete for planar graphs when the maximum vertex degree exceeds three. Using this result, we finally show that the via minimization problem, which arises in the design of integrated circuits and printed circuit boards, is NP-complete even when the maximum "junction" degree is limited to four.Item Reconfiguration for Programmable ASIC Arrays(1992) Narasimhan, Jagannathan; Nakajima, Kazuo; Rim, Chong S.; Dahbura, Anton T.; ISRIn an approach recently proposed for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. We first provide a graph theoretical formulation of the reconfiguration aspect of this approach. Based upon this formulation, we present three efficient algorithms. The first one optimally reconfigures the I/O buffers located on the periphery of a programmable array. The remaining algorithms are used as heuristics to reconfigure the gates located within a PGA and the processors within wafer scale integrated processor array. We evaluate the heuristic algorithms using the measure of routability and total wire length of the reconfigured placement of the circuit. Based on this evaluation, we establish good reconfiguration strategies.