Browsing by Author "Morgan, Brian"
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Item Development of a Deep Silicon Phase Fresnel Lens using Gray-scale Lithography and Deep Reactive Ion Etching(2004-04-22) Morgan, Brian; Ghodssi, Reza; Electrical EngineeringA phase Fresnel lens (PFL) could achieve higher sensitivity and angular resolution in astronomical observations than the current generation of gamma and hard x-ray instruments. For ground tests of a PFL system, silicon lenses must be fabricated on the micro-scale with controlled profiles to enable high lens efficiency. Thus, two MEMS-based technologies, gray-scale lithography and deep reactive ion etching (DRIE), are extended to create multiple controlled step heights in silicon on the necessary scale. A Gaussian approximation is introduced as a method of predicting a photoresist gray level height given the amount of transmitted light through a gray-scale optical mask. Etch selectivity during DRIE is then accurately controlled by introducing an oxygen-only step to a standard Bosch cycle to produce the desired scaling factor between the photoresist and silicon profiles. Finally, a profile evaluation method is developed to calculate the expected efficiency of measured silicon profiles. Calculated efficiencies above 87% have been achieved.Item Substrate interconnect technologies for 3-DMEMS packaging(2005) Morgan, Brian; Huab, Xuefeng; Iguchi, Tomohiro; Tomiokaf, Taizo; Oehrlein, Gottlieb S.; Ghodssi, Reza; ISRWe report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at d on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 lm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.